PIC18F44K20-I/P Microchip Technology, PIC18F44K20-I/P Datasheet - Page 122
![IC PIC MCU FLASH 8KX16 40DIP](/photos/6/61/66192/150-40-dip_sml.jpg)
PIC18F44K20-I/P
Manufacturer Part Number
PIC18F44K20-I/P
Description
IC PIC MCU FLASH 8KX16 40DIP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18F25K20T-ISS.pdf
(42 pages)
2.PIC18F25K20T-ISS.pdf
(12 pages)
3.PIC18F25K20T-ISS.pdf
(14 pages)
4.PIC18F25K20T-ISS.pdf
(456 pages)
5.PIC18F26K20-ISO.pdf
(430 pages)
Specifications of PIC18F44K20-I/P
Program Memory Type
FLASH
Program Memory Size
16KB (8K x 16)
Package / Case
40-DIP (0.600", 15.24mm)
Core Processor
PIC
Core Size
8-Bit
Speed
64MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
35
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 14x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
CCP/ECCP/EUSART/I2C/MSSP/SPI
Maximum Clock Frequency
64 MHz
Number Of Programmable I/os
36
Number Of Timers
4
Operating Supply Voltage
3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
14-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164112 - VOLTAGE LIMITER MPLAB ICD2 VPPDM164124 - KIT STARTER FOR PIC18F4XK20
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F44K20-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC18F44K20-I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC18F25K20T-ISS PDF datasheet
- PIC18F25K20T-ISS PDF datasheet #2
- PIC18F25K20T-ISS PDF datasheet #3
- PIC18F25K20T-ISS PDF datasheet #4
- PIC18F26K20-ISO PDF datasheet #5
- Current page: 122 of 456
- Download datasheet (4Mb)
PIC18F2XK20/4XK20
TABLE 10-1:
DS41303G-page 122
RA0/AN0/C12IN0-
RA1/AN1/C12IN1-
RA2/AN2/C2IN+
V
RA3/AN3/C1IN+/
V
RA4/T0CKI/C1OUT
RA5/AN4/SS/
HLVDIN/C2OUT
OSC2/CLKOUT/
RA6
Legend:
REF
REF
-/CV
+
Pin
REF
DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
PORTA I/O SUMMARY
Function
CLKOUT
C12IN0-
C12IN1-
HLVDIN
C1OUT
C2OUT
C2IN+
CV
C1IN+
V
T0CKI
OSC2
V
RA0
RA1
AN0
AN1
RA2
AN2
RA3
AN3
RA4
RA5
AN4
RA6
REF
REF
SS
REF
+
-
Setting
TRIS
0
1
1
1
0
1
1
1
0
1
1
1
1
x
0
1
1
1
1
0
1
1
0
0
1
1
1
1
0
0
1
x
x
I/O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Type
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
DIG
TTL
DIG
TTL
DIG
TTL
DIG
TTL
DIG
DIG
DIG
TTL
TTL
DIG
DIG
TTL
DIG
I/O
ST
ST
LATA<0> data output; not affected by analog input.
PORTA<0> data input; disabled when analog input enabled.
ADC input channel 0. Default input configuration on POR; does not
affect digital output.
Comparators C1 and C2 inverting input, channel 0. Analog select is
shared with ADC.
LATA<1> data output; not affected by analog input.
PORTA<1> data input; disabled when analog input enabled.
ADC input channel 1. Default input configuration on POR; does not
affect digital output.
Comparators C1 and C2 inverting input, channel 1. Analog select is
shared with ADC.
LATA<2> data output; not affected by analog input. Disabled when
CV
PORTA<2> data input. Disabled when analog functions enabled;
disabled when CV
ADC input channel 2. Default input configuration on POR; not affected
by analog output.
Comparator C2 non-inverting input. Analog selection is shared with
ADC.
ADC and comparator voltage reference low input.
Comparator voltage reference output. Enabling this feature disables
digital I/O.
LATA<3> data output; not affected by analog input.
PORTA<3> data input; disabled when analog input enabled.
A/D input channel 3. Default input configuration on POR.
Comparator C1 non-inverting input. Analog selection is shared with
ADC.
ADC and comparator voltage reference high input.
LATA<4> data output.
PORTA<4> data input; default configuration on POR.
Timer0 clock input.
Comparator 1 output; takes priority over port data.
LATA<5> data output; not affected by analog input.
PORTA<5> data input; disabled when analog input enabled.
A/D input channel 4. Default configuration on POR.
Slave select input for SSP (MSSP module).
Low-Voltage Detect external trip point input.
Comparator 2 output; takes priority over port data.
LATA<6> data output. Enabled in RCIO, INTIO2 and ECIO modes only.
PORTA<6> data input. Enabled in RCIO, INTIO2 and ECIO modes
only.
Main oscillator feedback output connection (XT, HS and LP modes).
System cycle clock output (F
modes.
REF
output enabled.
REF
output enabled.
OSC
Description
/4) in RC, INTIO1 and EC Oscillator
2010 Microchip Technology Inc.
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