ATMEGA164PA-MCH Atmel, ATMEGA164PA-MCH Datasheet - Page 133
![MCU AVR 16KB FLASH 20MHZ 44-VQFN](/photos/12/13/121316/313-44-qfn_sml.jpg)
ATMEGA164PA-MCH
Manufacturer Part Number
ATMEGA164PA-MCH
Description
MCU AVR 16KB FLASH 20MHZ 44-VQFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA164PA-MCH
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-VQFN Exposed Pad
For Use With
ATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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15.11 Register Description
15.11.1
8272A–AVR–01/10
TCCR1A – Timer/Counter1 Control Register A
Figure 15-13. Timer/Counter Timing Diagram, with Prescaler (f
• Bit 7:6 – COMnA1:0: Compare Output Mode for Channel A
• Bit 5:4 – COMnB1:0: Compare Output Mode for Channel B
The COMnA1:0 and COMnB1:0 control the Output Compare pins (OCnA and OCnB respec-
tively) behavior. If one or both of the COMnA1:0 bits are written to one, the OCnA output
overrides the normal port functionality of the I/O pin it is connected to. If one or both of the
COMnB1:0 bit are written to one, the OCnB output overrides the normal port functionality of the
I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit correspond-
ing to the OCnA or OCnB pin must be set in order to enable the output driver.
When the OCnA or OCnB is connected to the pin, the function of the COMnx1:0 bits is depen-
dent of the WGMn3:0 bits setting.
when the WGMn3:0 bits are set to a Normal or a CTC mode (non-PWM).
Table 15-2.
164A/164PA/324A/324PA/644A/644PA/1284/1284P
Bit
(0x80)
Read/Write
Initial Value
COMnA1/COMnB1
and ICF n
(PC and PFC PWM)
TOVn
(CTC and FPWM)
(Update at TOP)
0
0
1
1
TCNTn
TCNTn
OCRnx
(clk
as TOP)
clk
clk
I/O
(FPWM)
I/O
Tn
/8)
(if used
COM1A1
Compare Output Mode, non-PWM
R/W
7
0
COM1A0
COMnA0/COMnB0
R/W
6
0
TOP - 1
TOP - 1
Old OCRnx Value
0
1
0
1
COM1B1
Table 15-2 on page 133
R/W
5
0
COM1B0
R/W
4
0
Description
Normal port operation, OCnA/OCnB disconnected.
Toggle OCnA/OCnB on Compare Match.
Clear OCnA/OCnB on Compare Match (Set output to
low level).
Set OCnA/OCnB on Compare Match (Set output to
high level).
TOP
TOP
R
3
–
0
shows the COMnx1:0 bit functionality
BOTTOM
TOP - 1
clk_I/O
R
2
–
0
New OCRnx Value
/8)
WGM11
R/W
1
0
BOTTOM + 1
TOP - 2
WGM10
R/W
0
0
TCCR1A
133
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