DSPIC33FJ06GS202-E/SO Microchip Technology, DSPIC33FJ06GS202-E/SO Datasheet - Page 101
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DSPIC33FJ06GS202-E/SO
Manufacturer Part Number
DSPIC33FJ06GS202-E/SO
Description
IC DSPIC MCU/DSP 6K 28-SOIC
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.DSPIC33FJ06GS101-ISO.pdf
(346 pages)
2.DSPIC33FJ06GS101-ISO.pdf
(18 pages)
3.DSPIC33FJ06GS101-ISO.pdf
(16 pages)
Specifications of DSPIC33FJ06GS202-E/SO
Program Memory Type
FLASH
Program Memory Size
6KB (6K x 8)
Package / Case
28-SOIC (7.5mm Width)
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
21
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 6x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC33F
Core
dsPIC
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
21
Data Ram Size
1 KB
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC33FJ06GS202-E/SO
Manufacturer:
Microchip Technology
Quantity:
135
- DSPIC33FJ06GS101-ISO PDF datasheet
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- DSPIC33FJ06GS101-ISO PDF datasheet #3
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7.3
The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/
X04 devices implement 27 registers for the interrupt
controller:
• INTCON1
• INTCON2
• IFSx
• IECx
• IPCx
• INTTREG
7.3.1
Global interrupt control functions are controlled from
INTCON1 and INTCON2. INTCON1 contains the
Interrupt Nesting Disable (NSTDIS) bit as well as the
control and status flags for the processor trap sources.
The INTCON2 register controls the external interrupt
request signal behavior and the use of the Alternate
Interrupt Vector Table.
7.3.2
The IFSx registers maintain all of the interrupt request
flags. Each source of interrupt has a status bit, which is
set by the respective peripherals or external signal and
is cleared via software.
7.3.3
The IECx registers maintain all of the interrupt enable
bits. These control bits are used to individually enable
interrupts from the peripherals or external signals.
7.3.4
The IPCx registers are used to set the Interrupt Priority
Level for each source of interrupt. Each user interrupt
source can be assigned to one of eight priority levels.
© 2009 Microchip Technology Inc.
Interrupt Control and Status
Registers
INTCON1 AND INTCON2
IFSx
IECx
IPCx
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04
Preliminary
7.3.5
The INTTREG register contains the associated
interrupt vector number and the new CPU Interrupt
priority Level, which are latched into the Vector Number
(VECNUM<6:0>) and Interrupt Level (ILR<3:0>) bit
fields in the INTTREG register. The new Interrupt
Priority Level is the priority of the pending interrupt.
The interrupt sources are assigned to the IFSx, IECx
and IPCx registers in the same sequence that they are
listed in Table 7-1. For example, the INT0 (External
Interrupt 0) is shown as having vector number 8 and a
natural order priority of 0. Thus, the INT0IF bit is found
in IFS0<0>, the INT0IE bit is found in IEC0<0> and the
INT0IP bits are found in the first position of IPC0
(IPC0<2:0>).
7.3.6
Although they are not specifically part of the interrupt
control hardware, two of the CPU Control registers
contain bits that control interrupt functionality.
• The CPU STATUS register, SR, contains the
• The CORCON register contains the IPL3 bit,
All Interrupt registers are described in Register 7-1
through Register 7-35 in the following pages.
IPL<2:0> bits (SR<7:5>). These bits indicate the
current CPU interrupt Priority Level. The user can
change the current CPU priority level by writing to
the IPL bits.
which together with IPL<2:0>, indicates the
current CPU priority level. IPL3 is a read-only bit
so that trap events cannot be masked by the user
software.
INTTREG
STATUS/CONTROL REGISTERS
DS70318D-page 99
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