ATMEGA32A-MUR Atmel, ATMEGA32A-MUR Datasheet - Page 13
![MCU AVR 32KB FLASH 16MHZ 44QFN](/photos/12/13/121316/313-44-qfn_sml.jpg)
ATMEGA32A-MUR
Manufacturer Part Number
ATMEGA32A-MUR
Description
MCU AVR 32KB FLASH 16MHZ 44QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA32A-MU.pdf
(353 pages)
Specifications of ATMEGA32A-MUR
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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6.7
8155C–AVR–02/11
Reset and Interrupt Handling
Figure 6-5.
The Atmel
reset vector each have a separate program vector in the program memory space. All interrupts
are assigned individual enable bits which must be written logic one together with the Global
Interrupt Enable bit in the Status Register in order to enable the interrupt. Depending on the Pro-
gram Counter value, interrupts may be automatically disabled when Boot Lock bits BLB02 or
BLB12 are programmed. This feature improves software security. See the section
gramming” on page 267
The lowest addresses in the program memory space are by default defined as the Reset and
Interrupt Vectors. The complete list of vectors is shown in
determines the priority levels of the different interrupts. The lower the address the higher is the
priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request
0. The Interrupt Vectors can be moved to the start of the Boot Flash section by setting the IVSEL
bit in the General Interrupt Control Register (GICR). Refer to
information. The Reset Vector can also be moved to the start of the boot Flash section by pro-
gramming the BOOTRST fuse, see
Programming” on page
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are dis-
abled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled
interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a
Return from Interrupt instruction – RETI – is executed.
There are basically two types of interrupts. The first type is triggered by an event that sets the
Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vec-
tor in order to execute the interrupt handling routine, and hardware clears the corresponding
Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit position(s)
to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is
cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is
cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt
Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the
global interrupt enable bit is set, and will then be executed by order of priority.
The second type of interrupts will trigger as long as the interrupt condition is present. These
interrupts do not necessarily have Interrupt Flags. If the interrupt condition disappears before the
interrupt is enabled, the interrupt will not be triggered.
Register Operands Fetch
ALU Operation Execute
Total Execution Time
®
AVR
Result Write Back
Single Cycle ALU Operation
®
provides several different interrupt sources. These interrupts and the separate
clk
253.
for details.
CPU
“Boot Loader Support – Read-While-Write Self-
T1
T2
“Interrupts” on page
“Interrupts” on page 45
T3
ATmega32A
45. The list also
“Memory Pro-
T4
for more
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