PIC16F628A-I/ML Microchip Technology, PIC16F628A-I/ML Datasheet - Page 112
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PIC16F628A-I/ML
Manufacturer Part Number
PIC16F628A-I/ML
Description
IC MCU FLASH 2KX14 EEPROM 28QFN
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F627A-IP.pdf
(180 pages)
2.PIC16F627A-IP.pdf
(22 pages)
3.PIC16F648A-ISS.pdf
(178 pages)
Specifications of PIC16F628A-I/ML
Core Size
8-Bit
Program Memory Size
3.5KB (2K x 14)
Core Processor
PIC
Speed
20MHz
Connectivity
UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
224 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Controller Family/series
PIC16F
No. Of I/o's
16
Eeprom Memory Size
128Byte
Ram Memory Size
224Byte
Cpu Speed
20MHz
No. Of Timers
3
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
224 B
Interface Type
SCI, USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
16
Number Of Timers
1 x 16 bit
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014, DM164120-4
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164324 - MODULE SKT FOR MPLAB 8DFN/16QFNXLT28QFN3 - SOCKET TRAN ICE 18DIP/28QFNI3DBF648 - BOARD DAUGHTER ICEPIC3AC164033 - ADAPTER 28QFN TO 18DIPAC162053 - HEADER INTERFACE ICD,ICD2 18DIPDV007003 - PROGRAMMER UNIVERSAL PROMATE II
Data Converters
-
Lead Free Status / Rohs Status
Details
PIC16F627A/628A/648A
FIGURE 14-16:
TABLE 14-9:
14.8
The Power-down mode is entered by executing a
SLEEP instruction.
If enabled, the Watchdog Timer will be cleared but
keeps running, the PD bit in the Status register is
cleared, the TO bit is set, and the oscillator driver is
turned off. The I/O ports maintain the status they had,
before SLEEP was executed (driving high, low or high-
impedance).
DS40044G-page 112
Legend: x = unknown, u = unchanged, - = unimplemented read as ‘0’, q = value depends upon condition.
81h, 181h
Address
2007h
Note:
Note:
Power-Down Mode (Sleep)
Shaded cells are not used by the Watchdog Timer.
CONFIG
OPTION
Name
T0SE, T0CS, PSA, PS0-PS2 are bits in the OPTION register.
SUMMARY OF WATCHDOG TIMER REGISTERS
Enable Bit
Watchdog
WATCHDOG TIMER BLOCK DIAGRAM
RBPU INTEDG
Bit 7
LVP
Timer
WDT
From TMR0 Clock Source
BOREN MCLRE FOSC2
(Figure 6-1)
Bit 6
T0CS
Bit 5
PSA
0
1
M
U
X
T0SE
Bit 4
PWRTE
Bit 3
PSA
For lowest current consumption in this mode, all I/O
pins should be either at V
circuitry drawing current from the I/O pin and the
comparators, and V
that are high-impedance inputs should be pulled high
or low externally to avoid switching currents caused by
floating inputs. The T0CKI input should also be at V
or
contribution from on chip pull-ups on PORTB should be
considered.
The MCLR pin must be at a logic high level (V
0
WDT Postscaler/
TMR0 Prescaler
Time-out
Note:
MUX
WDT
WDTE
Bit 2
V
8 to 1 MUX
PS2
SS
1
8
for
It should be noted that a Reset generated
by a WDT time-out does not drive MCLR
pin low.
FOSC1
Bit 1
PS1
lowest
PSA
3
(Figure 6-1)
REF
PS<2:0>
To TMR0
FOSC0 uuuu uuuu uuuu uuuu
Bit 0
PS0
© 2009 Microchip Technology Inc.
current
should be disabled. I/O pins
DD
1111 1111 1111 1111
or V
POR Reset
Value on
consumption.
SS
with no external
Value on
all other
Resets
IHMC
The
).
DD