PIC16C62B-20I/SO Microchip Technology, PIC16C62B-20I/SO Datasheet - Page 54
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PIC16C62B-20I/SO
Manufacturer Part Number
PIC16C62B-20I/SO
Description
IC MCU OTP 2KX14 PWM 28SOIC
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Datasheets
1.PIC16F818-ISO.pdf
(6 pages)
2.PIC16C62B-04SO.pdf
(120 pages)
3.PIC16C62B-04SO.pdf
(5 pages)
4.PIC16C62A-04SP.pdf
(337 pages)
Specifications of PIC16C62B-20I/SO
Core Size
8-Bit
Program Memory Size
3.5KB (2K x 14)
Oscillator Type
External
Core Processor
PIC
Speed
20MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Type
OTP
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Controller Family/series
PIC16C
No. Of I/o's
22
Ram Memory Size
128Byte
Cpu Speed
20MHz
No. Of Timers
3
No. Of Pwm
RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16C62B-20I/SO
Manufacturer:
Microchip Technology
Quantity:
135
Part Number:
PIC16C62B-20I/SO
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
PIC16C62B/72A
9.4
9.5
An A/D conversion can be started by the “special event
trigger” of the CCP1 module. This requires that the
CCP1M3:CCP1M0 bits (CCP1CON<3:0>) be pro-
grammed as 1011 and that the A/D module be enabled
(ADON bit is set). When the trigger occurs, the
TABLE 9-2
DS35008B-page 54
Address Name
0Bh,8Bh
0Ch
8Ch
1Eh
1Fh
9Fh
05h
85h
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used for A/D conversion.
Note:
A/D Conversions
Use of the CCP Trigger
INTCON
PIR1
PIE1
ADRES
ADCON0 ADCS1 ADCS0
ADCON1
PORTA
TRISA
The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
SUMMARY OF A/D REGISTERS
A/D Result Register
Bit 7
GIE
—
—
—
—
—
ADIF
ADIE
Bit 6
PEIE
—
—
—
PORTA Data Direction Register
CHS2
Bit 5
T0IE
RA5
—
—
—
CHS1
INTE
Bit 4
RA4
—
—
—
Preliminary
SSPIF
SSPIE
CHS0
RBIE
Bit 3
RA3
—
GO/DONE bit will be set, starting the A/D conversion,
and the Timer1 counter will be reset to zero. Timer1 is
reset to automatically repeat the A/D acquisition period
with minimal software overhead. The appropriate ana-
log input channel must be selected and the minimum
acquisition time must pass before the “special event
trigger” sets the GO/DONE bit (starts a conversion).
If the A/D module is not enabled (ADON is cleared),
then the “special event trigger” will be ignored by the
A/D module, but will still reset the Timer1 counter.
GO/DONE
CCP1IE
CCP1IF
PCFG2
Bit 2
T0IF
RA2
TMR2IF TMR1IF -0-- 0000
TMR2IE TMR1IE -0-- 0000
PCFG1
INTF
Bit 1
RA1
—
PCFG0 ---- -000
ADON
RBIF
Bit 0
RA0
1999 Microchip Technology Inc.
0000 000x
xxxx xxxx
0000 00-0
--0x 0000
--11 1111
Value on
POR,
BOR
other Resets
Value on all
0000 000u
-0-- 0000
-0-- 0000
uuuu uuuu
0000 00-0
---- -000
--0u 0000
--11 1111