PIC16C432-E/SS Microchip Technology, PIC16C432-E/SS Datasheet - Page 55

• Manufacturer Part Number: PIC16C432-E/SS
• Description: IC MCU CMOS 8BIT 20MHZ 2K 20SSOP
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C432-E/SS

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: LIN (Local Interconnect Network)
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 12
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: OTP
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 20-SSOP
• For Use With: XLT20SS-1 - SOCKET TRANSITION 18DIP 20SSOPAC164307 - MODULE SKT FOR PM3 28SSOPAC164029 - MODULE SKT PROMATEII 20DIP/SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

9.5
The PIC16C432 has 4 sources of interrupt:
• External interrupt RB0/INT
• TMR0 overflow interrupt
• PORTB change interrupts (pins RB<7:4>)
• Comparator interrupt
• LIN Bus wake-up can be wired to RB0, or compar-
The interrupt control register (INTCON) and the Periph-
eral Interrupt Register (PIR1) record individual interrupt
requests in flag bits. INTCON and PIR1 have individual
and global interrupt enable bits.
A global interrupt enable bit, GIE (INTCON<7>)
enables (if set) all un-masked interrupts, or disables (if
cleared) all interrupts. Individual interrupts can be
disabled through their corresponding enable bits in
INTCON register. GIE is cleared on RESET.
The “return from interrupt” instruction,
interrupt routine, as well as sets the GIE bit, which re-
enables all unmasked interrupts.
The INT pin interrupt, the RB port change interrupt and
the TMR0 overflow interrupt flags are contained in the
INTCON register.
The peripheral interrupt flag is contained in the special
register PIR1. The corresponding interrupt enable bit is
contained in special registers PIE1.
FIGURE 9-15:
ator
2002 Microchip Technology Inc.
Interrupts
CMIE
CMIF
INTERRUPT LOGIC
INTE
PEIE
INTF
T0IE
RBIE
T0IF
RBIF
GIE
RETFIE
, exits
Preliminary
When an interrupt is responded to, the GIE is cleared
to disable any further interrupt, the return address is
pushed into the stack and the PC is loaded with 0004h.
Once in the Interrupt Service Routine, the source(s) of
the interrupt can be determined by polling the interrupt
flag bits. The interrupt flag bit(s) must be cleared in soft-
ware before re-enabling interrupts to avoid RB0/INT
recursive interrupts.
For external interrupt events, such as the INT pin or
PORTB change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends on when the interrupt event occurs (Figure 9-
16). The latency is the same for one or two cycle
instructions. Once in the Interrupt Service Routine, the
source(s) of the interrupt can be determined by polling
the interrupt flag bits. The interrupt flag bit(s) must be
cleared in software before re-enabling interrupts to
avoid multiple interrupt requests.
Note 1: Individual interrupt flag bits are set, regard-
2: When an instruction that clears the GIE bit
less of the status of their corresponding
mask bit or the GIE bit.
is executed, any interrupts that were
pending for execution in the next cycle are
ignored. The CPU will execute a NOP in the
cycle immediately following the instruction
which clears the GIE bit. The interrupts
which were ignored are still pending to be
serviced when the GIE bit is set again.
(If in SLEEP mode)
Wake-up
PIC16C432
Interrupt
to CPU
DS41140B-page 53