PIC18F65J10-I/PT Microchip Technology, PIC18F65J10-I/PT Datasheet - Page 193

• Manufacturer Part Number: PIC18F65J10-I/PT
• Description: IC PIC MCU FLASH 16KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F65J10-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 32KB (16K x 16)
• Package / Case: 64-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 50
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SPI/I2C/EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 50
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183022, DM183032
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 11-ch x 10-bit
• Package: 64TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA180015 - MODULE PLUG-IN 18F87J10 FOR HPCAC162062 - HEADER INTRFC MPLAB ICD2 64/80PAC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

REGISTER 18-2:
© 2006 Microchip Technology Inc.
bit 7
bit 6
bit 5
bit 4
bit 3-0
SSPxCON1: MSSPx CONTROL REGISTER 1 (SPI MODE)
bit 7
WCOL: Write Collision Detect bit
1 = The SSPxBUF register is written while it is still transmitting the previous word
0 = No collision
SSPOV: Receive Overflow Indicator bit
SPI Slave mode:
1 = A new byte is received while the SSPxBUF register is still holding the previous data. In case
0 = No overflow
SSPEN: Master Synchronous Serial Port Enable bit
1 = Enables serial port and configures SCKx, SDOx, SDIx and SSx as serial port pins
0 = Disables serial port and configures these pins as I/O port pins
CKP: Clock Polarity Select bit
1 = Idle state for clock is a high level
0 = Idle state for clock is a low level
SSPM3:SSPM0: Master Synchronous Serial Port Mode Select bits
0101 = SPI Slave mode, clock = SCKx pin, SSx pin control disabled, SSx can be used as I/O pin
0100 = SPI Slave mode, clock = SCKx pin, SSx pin control enabled
0011 = SPI Master mode, clock = TMR2 output/2
0010 = SPI Master mode, clock = F
0001 = SPI Master mode, clock = F
0000 = SPI Master mode, clock = F
Legend:
R = Readable bit
-n = Value at POR
WCOL
R/W-0
Note:
Note:
Note:
(must be cleared in software)
of overflow, the data in SSPxSR is lost. Overflow can only occur in Slave mode. The user
must read the SSPxBUF, even if only transmitting data, to avoid setting overflow (must be
cleared in software).
In Master mode, the overflow bit is not set since each new reception (and
transmission) is initiated by writing to the SSPxBUF register.
When enabled, these pins must be properly configured as input or output.
Bit combinations not specifically listed here are either reserved or implemented in
I
2
SSPOV
C mode only.
R/W-0
W = Writable bit
‘1’ = Bit is set
SSPEN
R/W-0
Preliminary
OSC
OSC
OSC
R/W-0
CKP
/64
/16
/4
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
SSPM3
R/W-0
PIC18F87J10
SSPM2
R/W-0
x = Bit is unknown
SSPM1
R/W-0
DS39663D-page 191
SSPM0
R/W-0
bit 0