ATMEGA8A-PU Atmel, ATMEGA8A-PU Datasheet - Page 305
![MCU AVR 8K FLASH 16MHZ 28-PDIP](/photos/7/21/72189/453-28-dip_sml.jpg)
ATMEGA8A-PU
Manufacturer Part Number
ATMEGA8A-PU
Description
MCU AVR 8K FLASH 16MHZ 28-PDIP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA8A-PU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Processor Series
ATMEGA8x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
SPI, TWI, USART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
23
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 6 Channel
Package
28PDIP
Device Core
AVR
Family Name
ATmega
Maximum Speed
16 MHz
Operating Supply Voltage
3.3|5 V
Controller Family/series
AVR MEGA
No. Of I/o's
23
Eeprom Memory Size
512Byte
Ram Memory Size
1KB
Cpu Speed
16MHz
Rohs Compliant
Yes
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA8A-PU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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8159D–AVR–02/11
19 USART ................................................................................................... 136
20 Two-wire Serial Interface ..................................................................... 165
21 Analog Comparator ............................................................................. 195
22 Analog-to-Digital Converter ................................................................ 198
18.4
18.5
19.1
19.2
19.3
19.4
19.5
19.6
19.7
19.8
19.9
19.10
19.11
20.1
20.2
20.3
20.4
20.5
20.6
20.7
20.8
21.1
21.2
21.3
22.1
22.2
22.3
22.4
22.5
22.6
22.7
Data Modes ...................................................................................................131
Register Description ......................................................................................133
Features ........................................................................................................136
Overview ........................................................................................................136
Clock Generation ...........................................................................................138
Frame Formats ..............................................................................................141
USART Initialization .......................................................................................142
Data Transmission – The USART Transmitter ..............................................143
Asynchronous Data Reception ......................................................................150
Multi-processor Communication Mode ..........................................................153
Accessing UBRRH/UCSRC Registers ..........................................................154
Register Description ......................................................................................156
Examples of Baud Rate Setting .....................................................................161
Features ........................................................................................................165
Overview ........................................................................................................165
Two-wire Serial Interface Bus Definition ........................................................167
Data Transfer and Frame Format ..................................................................168
Multi-master Bus Systems, Arbitration and Synchronization .........................171
Using the TWI ................................................................................................173
Multi-master Systems and Arbitration ............................................................190
Register Description ......................................................................................191
Overview ........................................................................................................195
Analog Comparator Multiplexed Input ...........................................................195
Register Description ......................................................................................196
Features ........................................................................................................198
Overview ........................................................................................................198
Starting a Conversion ....................................................................................200
Prescaling and Conversion Timing ................................................................200
Changing Channel or Reference Selection ...................................................202
ADC Noise Canceler .....................................................................................203
ADC Conversion Result .................................................................................207
ATmega8A
iv
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