PIC16LF88T-I/ML Microchip Technology, PIC16LF88T-I/ML Datasheet - Page 44
![IC MCU FLASH 4KX14 EEPROM 28QFN](/photos/6/81/68120/150-28-qfn_sml.jpg)
PIC16LF88T-I/ML
Manufacturer Part Number
PIC16LF88T-I/ML
Description
IC MCU FLASH 4KX14 EEPROM 28QFN
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16LF627A-IP.pdf
(8 pages)
2.PIC16F818-ISO.pdf
(6 pages)
3.PIC16F87-IP.pdf
(228 pages)
4.PIC16F87-IP.pdf
(8 pages)
5.PIC16F87-IP.pdf
(4 pages)
6.PIC16F87-IP.pdf
(8 pages)
Specifications of PIC16LF88T-I/ML
Core Processor
PIC
Core Size
8-Bit
Speed
10MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
7KB (4K x 14)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
368 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 7x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Processor Series
PIC16LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
368 B
Interface Type
SSP, USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
16
Number Of Timers
8
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- PIC16LF627A-IP PDF datasheet
- PIC16F818-ISO PDF datasheet #2
- PIC16F87-IP PDF datasheet #3
- PIC16F87-IP PDF datasheet #4
- PIC16F87-IP PDF datasheet #5
- PIC16F87-IP PDF datasheet #6
- Current page: 44 of 228
- Download datasheet (5Mb)
PIC16F87/88
• Clock before switch: One of INTOSC/INTOSC
1.
2.
3.
4.
5.
TABLE 4-3:
DS30487C-page 42
Note 1:
INTRC/Sleep
postscaler (IRCF<2:0>
(31.25 kHz)
(31.25 kHz)
Sleep/POR
IRCF bits are modified to a different INTOSC/
INTOSC postscaler frequency.
edge of the current clock, at which point CLKO
is held low.
The clock switching circuitry then waits for eight
falling edges of requested clock, after which it
switches CLKO to this new clock source.
The IOFS bit is set.
Oscillator switchover is complete.
The clock switching circuitry waits for a falling
INTRC
INTRC
From
Sleep
Clock Switch
The 5-10 s start-up delay is based on a 1 MHz system clock.
LP, XT, HS 32.768 kHz-20 MHz
Postscaler
Postscaler
INTOSC/
INTOSC/
INTOSC
INTOSC
OSCILLATOR DELAY EXAMPLES
T1OSC
EC, RC
EC, RC
INTRC
To
000)
125 kHz-8 MHz
125 kHz-8 MHz
DC – 20 MHz
DC – 20 MHz
Frequency
32.768 kHz
31.25 kHz
4 ms (approx.) and
1024 Clock Cycles
Oscillator Delay
CPU Start-up
CPU Start-up
4 ms (approx.)
(OST)
4.6.6
Table 4-3 shows the different delays invoked for
various clock switching sequences. It also shows the
delays invoked for POR and wake-up.
(1)
(1)
Following a wake-up from Sleep mode or
POR, CPU start-up is invoked to allow the
CPU to become ready for code execution.
Following a change from INTRC, an OST
of 1024 cycles must occur.
Refer to Section 4.6.4 “Modifying the
IRCF Bits” for further details.
OSCILLATOR DELAY UPON
POWER-UP, WAKE-UP AND
CLOCK SWITCHING
2005 Microchip Technology Inc.
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