PIC16LF88T-I/ML Microchip Technology, PIC16LF88T-I/ML Datasheet - Page 45
![IC MCU FLASH 4KX14 EEPROM 28QFN](/photos/6/81/68120/150-28-qfn_sml.jpg)
PIC16LF88T-I/ML
Manufacturer Part Number
PIC16LF88T-I/ML
Description
IC MCU FLASH 4KX14 EEPROM 28QFN
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16LF627A-IP.pdf
(8 pages)
2.PIC16F818-ISO.pdf
(6 pages)
3.PIC16F87-IP.pdf
(228 pages)
4.PIC16F87-IP.pdf
(8 pages)
5.PIC16F87-IP.pdf
(4 pages)
6.PIC16F87-IP.pdf
(8 pages)
Specifications of PIC16LF88T-I/ML
Core Processor
PIC
Core Size
8-Bit
Speed
10MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
7KB (4K x 14)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
368 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 7x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Processor Series
PIC16LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
368 B
Interface Type
SSP, USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
16
Number Of Timers
8
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- PIC16LF627A-IP PDF datasheet
- PIC16F818-ISO PDF datasheet #2
- PIC16F87-IP PDF datasheet #3
- PIC16F87-IP PDF datasheet #4
- PIC16F87-IP PDF datasheet #5
- PIC16F87-IP PDF datasheet #6
- Current page: 45 of 228
- Download datasheet (5Mb)
4.7
4.7.1
When SCS bits are configured to run from the INTRC,
a clock transition is generated if the system clock is
not already using the INTRC. The event will clear the
OSTS bit, switch the system clock from the primary
system clock (if SCS<1:0> = 00) determined by the
value contained in the configuration bits, or from the
T1OSC (if SCS<1:0> = 01) to the INTRC clock option
and shut down the primary system clock to conserve
power. Clock switching will not occur if the primary
system clock is already configured as INTRC.
FIGURE 4-7:
2005 Microchip Technology Inc.
Note 1:
SCS<1:0>
Program
INTOSC
Counter
System
OSC1
Clock
2:
3:
4:
Power-Managed Modes
T
T
T
T
Q1
OSC
SCS
INP
DLY
RC_RUN MODE
T
Q2
OSC (2)
= 32 s typical.
= 50 ns minimum.
= 8 T
= 1 T
PC
Q3
INP
INP
Q4
.
.
TIMING DIAGRAM FOR XT, HS, LP, EC AND EXTRC TO RC_RUN MODE
Q1
T
DLY
(4)
T
INP
(1)
T
SCS (3)
PC + 1
If the system clock does not come from the INTRC
(31.25 kHz) when the SCS bits are changed and the
IRCF bits in the OSCCON register are configured for a
frequency other than INTRC, the frequency may not be
stable immediately. The IOFS bit (OSCCON<2>) will
be set when the INTOSC or postscaler frequency is
stable, after 4 ms (approx.).
After a clock switch has been executed, the OSTS bit
is cleared, indicating a low-power mode and the
device does not run from the primary system clock.
The internal Q clocks are held in the Q1 state until
eight falling edge clocks are counted on the INTRC
oscillator.
transpired, the clock input to the Q clocks is released
and operation resumes (see Figure 4-7).
Q1
Q2
After
Q3
the
Q4
PIC16F87/88
eight
Q1
clock
Q2
PC + 2
DS30487C-page 43
Q3
periods
Q4
PC + 3
Q1
have
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