ATMEGA32U4-MUR Atmel, ATMEGA32U4-MUR Datasheet - Page 169
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ATMEGA32U4-MUR
Manufacturer Part Number
ATMEGA32U4-MUR
Description
MCU AVR 16K FLASH 16MHZ 44VQFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA16U4-MU.pdf
(433 pages)
Specifications of ATMEGA32U4-MUR
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
26
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2.5K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-VQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA32U4-MUR
Manufacturer:
UCC
Quantity:
1 001
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- Download datasheet (9Mb)
15.12.5
7766F–AVR–11/10
TCCR4E – Timer/Counter4 Control Register E
• Bit 3 - FPAC4: Fault Protection Analog Comparator Enable
When written logic one, this bit enables the Fault Protection function in Timer/Counter4 to be
triggered by the Analog Comparator. The comparator output is in this case directly connected to
the Fault Protection front-end logic, making the comparator utilize the noise canceler and edge
select features of the Timer/Counter4 Fault Protection interrupt. When written logic zero, no con-
nection between the Analog Comparator and the Fault Protection function exists. To make the
comparator trigger the Timer/Counter4 Fault Protection interrupt, the FPIE4 bit in the
Timer/Counter4 Control Register D (TCCR4D) must be set.
• Bit 2- FPF4: Fault Protection Interrupt Flag
When the FPIE4 bit is set (one), the Fault Protection Interrupt is enabled. Activity on the pin will
cause an interrupt request even, if the Fault Protection pin is configured as an output. The corre-
sponding interrupt of Fault Protection Interrupt Request is executed from the Fault Protection
Interrupt Vector. The bit FPF4 is cleared by hardware when executing the corresponding inter-
rupt handling vector. Alternatively, FPF4 is cleared after a synchronization clock cycle by writing
a logical one to the flag. When the SREG I-bit, FPIE4 and FPF4 are set, the Fault Interrupt is
executed.
• Bits 1:0 - WGM41, WGM40: Waveform Generation Mode Bits
This bit associated with the PWM4x bits control the counting sequence of the counter, the
source for type of waveform generation to be used, see
ported by the Timer/Counter4 are: Normal mode (counter), Fast PWM Mode, Phase and
Frequency Correct PWM and PWM6 Modes.
Table 15-19. Waveform Generation Mode Bit Description
• Bit 7 - TLOCK4: Register Update Lock
This bit controls the Compare registers update. When this bit is set, writing to the Compare reg-
isters will not affect the output, however the values are stored and will be updated to the
Compare registers when the TLOCK4 bit will be cleared.
Refer to
Bit
Read/Write
Initial value
PWM4x
0
1
1
1
1
Section 15.7 ”Synchronous update” on page 149
WGM41..40
TLOCK4
00
01
10
11
xx
R
7
0
ENHC4
Timer/Counter Mode of Operation
Normal
Fast PWM
Phase and Frequency Correct PWM
PWM6 / Single-slope
PWM6 / Dual-slope
R
6
0
OC4OE5
R/W
5
0
OC4OE4
R/W
4
0
OC4OE3
R/W
3
0
Table
for more details.
OC4OE2
TOP
OCR4C
OCR4C
OCR4C
OCR4C
OCR4C
R/W
2
0
15-19. Modes of operation sup-
ATmega16/32U4
OC4OE1
R/W
1
0
Update of
OCR4x at
Immediate
TOP
BOTTOM
TOP
BOTTOM
OC4OE0
R/W
0
0
TOV4 Flag
Set on
TOP
TOP
BOTTOM
TOP
BOTTOM
TCCR4E
169
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