PIC16F73T-E/SS Microchip Technology, PIC16F73T-E/SS Datasheet - Page 269
![IC MCU FLASH 4KX14 A/D 28SSOP](/photos/6/81/68119/150-28-ssop_sml.jpg)
PIC16F73T-E/SS
Manufacturer Part Number
PIC16F73T-E/SS
Description
IC MCU FLASH 4KX14 A/D 28SSOP
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F688T-ISL.pdf
(688 pages)
3.PIC16F818-ISO.pdf
(6 pages)
4.PIC16F73-ISP.pdf
(174 pages)
5.PIC16F73-ISP.pdf
(14 pages)
6.PIC16F73-ISP.pdf
(12 pages)
Specifications of PIC16F73T-E/SS
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
7KB (4K x 14)
Program Memory Type
FLASH
Ram Size
192 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 5x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
28-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
PIC16F73TE/SS
- PIC16F616T-ISL PDF datasheet
- PIC16F688T-ISL PDF datasheet #2
- PIC16F818-ISO PDF datasheet #3
- PIC16F73-ISP PDF datasheet #4
- PIC16F73-ISP PDF datasheet #5
- PIC16F73-ISP PDF datasheet #6
- Current page: 269 of 688
- Download datasheet (3Mb)
16.4.1.2
SDA
SCL
SSPIF
1997 Microchip Technology Inc.
BF (SSPSTAT<0>)
SSPOV (SSPCON<6>)
S
Reception
A7 A6 A5 A4 A3 A2 A1
1
2
Receiving Address
3
When the R/W bit of the address byte is clear and an address match occurs, the R/W bit of the
SSPSTAT register is cleared. The received address is loaded into the SSPBUF register.
When the address byte overflow condition exists, then no acknowledge (ACK) pulse is given. An
overflow condition is defined as either the BF bit (SSPSTAT<0>) is set or the SSPOV bit
(SSPCON<6>) is set.
An SSP interrupt is generated for each data transfer byte. The SSPIF flag bit must be cleared in
software, and the SSPSTAT register is used to determine the status of the byte.
Figure 16-8:
4
5
6
7
R/W=0
8
I
2
C Waveforms for Reception (7-bit Address)
ACK
9
D7
1
D6
2
SSPBUF register is read
Cleared in software
Receiving Data
D5
3
D4
Bit SSPOV is set because the SSPBUF register is still full.
4
D3
5
D2
6
D1
7
D0
8
ACK
Section 16. BSSP
9
D7
1
D6
2
D5
Receiving Data
3
D4
4
ACK is not sent.
D3
5
D2
6
D1
7
DS31016A-page 16-19
D0
8
ACK
9
transfer
Bus Master
terminates
P
16
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