PIC18F2321-I/SS Microchip Technology, PIC18F2321-I/SS Datasheet - Page 66

• Manufacturer Part Number: PIC18F2321-I/SS
• Description: IC PIC MCU FLASH 4KX16 28SSOP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2321-I/SS

• Core Size: 8-Bit
• Program Memory Size: 8KB (4K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SSOP
• Controller Family/series: PIC18
• No. Of I/o's: 25
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 512Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: EUSART, I2C, MSSP, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, ICE2000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 10 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164307 - MODULE SKT FOR PM3 28SSOP
• Lead Free Status / Rohs Status: Details

PIC18F4321 FAMILY
TABLE 5-2:
DS39689E-page 64
TMR0H
TMR0L
T0CON
OSCCON
HLVDCON
WDTCON
RCON
TMR1H
TMR1L
T1CON
TMR2
PR2
T2CON
SSPBUF
SSPADD
SSPSTAT
SSPCON1
SSPCON2
ADRESH
ADRESL
ADCON0
ADCON1
ADCON2
CCPR1H
CCPR1L
CCP1CON
CCPR2H
CCPR2L
CCP2CON
BAUDCON
ECCP1DEL
ECCP1AS
CVRCON
CMCON
TMR3H
TMR3L
T3CON
Legend:
Note
File Name
1:
2:
3:
4:
5:
6:
Timer0 Register High Byte
Timer0 Register Low Byte
Timer1 Register High Byte
Timer1 Register Low Byte
Timer2 Register
Timer2 Period Register
MSSP Receive Buffer/Transmit Register
MSSP Address Register in I
A/D Result Register High Byte
A/D Result Register Low Byte
Capture/Compare/PWM Register 1 High Byte
Capture/Compare/PWM Register 1 Low Byte
Capture/Compare/PWM Register 2 High Byte
Capture/Compare/PWM Register 2 Low Byte
Timer3 Register High Byte
Timer3 Register Low Byte
x = unknown, u = unchanged, — = unimplemented, q = value depends on condition
The SBOREN bit is only available when the BOREN1:BOREN0 Configuration bits = 01; otherwise, it is disabled and reads as ‘0’. See
Section 4.4 “Brown-out Reset (BOR)”.
These registers and/or bits are not implemented on 28-pin devices and are read as
individual unimplemented bits should be interpreted as ‘-’.
The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as
INTOSC Modes”.
The RE3 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit = 0); otherwise, RE3 reads as
read-only.
RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes.
When disabled, these bits read as ‘0’.
Bit 7 and bit 6 are cleared by user software or by a POR.
VDIRMAG
ECCPASE
TMR0ON
ABDOVF
P1M1
PRSEN
CVREN
C2OUT
WCOL
IDLEN
GCEN
ADFM
RD16
RD16
IPEN
Bit 7
SMP
—
—
—
—
—
(2)
REGISTER FILE SUMMARY (PIC18F2221/2321/4221/4321) (CONTINUED)
SBOREN
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0
ECCPAS2
ACKSTAT
T3CCP2
PDC6
P1M0
CVROE
T08BIT
T1RUN
SSPOV
C1OUT
RCIDL
IRCF2
Bit 6
CKE
—
—
—
—
—
—
(2)
(2)
(1)
2
C™ Slave mode. MSSP Baud Rate Reload Register in I
ECCPAS1
T1CKPS1
T3CKPS1
ADMSK5
ACKDT/
PDC5
RXDTP
SSPEN
VCFG1
ACQT2
DC1B1
DC2B1
IRCF1
IRVST
C2INV
CVRR
T0CS
CHS3
Bit 5
D/A
—
—
(2)
ECCPAS0
T1CKPS0
T3CKPS0
ADMSK4
HLVDEN
ACKEN/
PDC4
VCFG0
ACQT1
TXCKP
CVRSS
DC1B0
DC2B0
IRCF0
C1INV
CHS2
T0SE
Bit 4
CKP
—
RI
P
(2)
Preliminary
T1OSCEN
ADMSK3
CCP1M3
CCP2M3
PSSAC1
T3CCP1
HLVDL3
PDC3
SSPM3
PCFG3
ACQT0
BRG16
RCEN/
OSTS
CHS1
CVR3
Bit 3
PSA
CIS
TO
—
S
(2)
TMR2ON
ADMSK2
CCP1M2
CCP2M2
T1SYNC
PSSAC0
T3SYNC
HLVDL2
PDC2
SSPM2
PCFG2
ADCS2
T0PS2
CHS0
CVR2
IOFS
PEN/
Bit 2
CM2
R/W
PD
—
—
(2)
‘
0
2
PSSBD1
’
C Master mode.
GO/DONE
T2CKPS1
. Reset values are shown for 40/44-pin devices;
TMR1CS
ADMSK1
CCP1M1
CCP2M1
TMR3CS
HLVDL1
PDC1
SSPM1
PCFG1
ADCS1
T0PS1
RSEN/
CVR1
SCS1
WUE
Bit 1
POR
CM1
UA
—
(2)
(2)
© 2007 Microchip Technology Inc.
PSSBD0
SWDTEN
T2CKPS0
TMR1ON
TMR3ON
CCP1M0
CCP2M0
HLVDL0
PDC0
SSPM0
PCFG0
ADCS0
ABDEN
T0PS0
ADON
SCS0
CVR0
Bit 0
BOR
SEN
CM0
BF
‘
0
’
(2)
. See Section 2.6.4 “PLL in
(2)
0000 0000
xxxx xxxx
1111 1111
0100 q000
0-00 0101
0q-1 11q0 42, 48, 102
xxxx xxxx
xxxx xxxx
0000 0000
0000 0000
1111 1111
-000 0000
xxxx xxxx
0000 0000
0000 0000
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
--00 0000
--00 0qqq
0-00 0000
xxxx xxxx
xxxx xxxx
0000 0000
xxxx xxxx
xxxx xxxx
--00 0000
0100 0-00
0000 0000
0000 0000
0000 0000
0000 0111
xxxx xxxx
xxxx xxxx
0000 0000
POR, BOR
--- ---0
Value on
‘
0
’
. This bit is
Details on
50, 169,
50, 162,
50, 163,
51, 139,
50, 125
50, 125
50, 123
50, 247
50, 264
50, 131
50, 131
50, 127
50, 134
50, 134
50, 133
50, 170
50, 173
51, 236
51, 236
51, 227
51, 228
51, 229
51, 140
51, 140
51, 140
51, 140
51, 139
51, 208
51, 156
51, 157
51, 243
51, 237
51, 137
51, 137
51, 135
page:
31, 50
170
171
172
147