AT32UC3L032-AUR Atmel, AT32UC3L032-AUR Datasheet - Page 58

• Manufacturer Part Number: AT32UC3L032-AUR
• Description: IC MCU AVR32 32K FLASH 48TQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3L032-AUR

• Package / Case: 48-TQFP, 48-VQFP
• Voltage - Supply (vcc/vdd): 1.62 V ~ 1.98 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 50MHz
• Number Of I /o: 36
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Program Memory Size: 32KB (32K x 8)
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, DMA, PWM, WDT
• Connectivity: I²C, SPI, UART/USART
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

10.2.2
10.2.3
10.2.4
32099AS–AVR32–06/09
FLASHCDW
HMATRIX
PDCA
1. Chip erase
2. Fuse programming
3. Wait 500 ns before reading from the flash after switching read mode
4. VERSION register reads 0x100
1. In the HMATRIX PRAS and PRBS registers MxPR fields are only two bits
1. PCONTROL.CHxRES is nonfunctional
2. Transfer error will stall a transmit peripheral handshake interface.
3. VERSION register reads 0x120
atomically. Even if this step is described in general as not safe in the UC technical reference
manual, it is safe in this very specific case.
2. Execute the RETE instruction.
When performing chip erase, the device may report that it is protected (IR=0x11) and that
chiperase failed, even if the chip erase was succesful.
Fix/workaround
Perform a reset before any further read and programming.
Programming of fuses does not work.
Fix/workaround
Do not program fuses. All fuses will be erased during chiperase command.
After switching between normal read mode and high-speed read mode, the application must
wait at least 500 ns before attempting any access to the flash.
Fix/workaround
Two workarounds exist:
1. Make sure that the appropriate instructions are executed from RAM, and that a waiting-
loop is executed from RAM waiting 500ns or more before executing from flash.
2. Execute from flash with a clock with period longer than 500 ns. This guarantees that no
new read access is attempted before the flash has had time to settle in the new read mode.
The VERSION register reads 0x100 instead of 0x102.
Fix/Workaround
None.
In the HMATRIX PRAS and PRBS registers MxPR fields are only two bits wide, instead of
four bits. The unused bits are undefined when reading the registers.
Fix/Workaround
Mask undefined bits when reading PRAS and PRBS.
PCONTROL.CHxRES is nonfunctional. Counters are reset at power-on, and cannot be
reset by software.
Fix/Workaround
SW needs to keep history of performance counters.
If a transfer error is encountered on a channel transmitting to a peripheral, the peripheral
handshake of the active channel will stall and the PDCA will not do any more transfers on
the affected peripheral handshake interface.
Fix/workaround
Disable and then enable the peripheral after the transfer error.
The VERSION register reads 0x120 instead of 0x122.
AT32UC3L
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