PIC18F2221-I/ML Microchip Technology, PIC18F2221-I/ML Datasheet - Page 312

• Manufacturer Part Number: PIC18F2221-I/ML
• Description: IC PIC MCU FLASH 2KX16 28QFN
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2221-I/ML

• Core Size: 8-Bit
• Program Memory Size: 4KB (2K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Controller Family/series: PIC18
• No. Of I/o's: 25
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 512Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Package: 28QFN EP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 25
• Interface Type: I2C/SPI/USART
• On-chip Adc: 10-chx10-bit
• Number Of Timers: 4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT28QFN4 - SOCKET TRANS ICE 28QFN W/CABLEAC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC18F2221/2321/4221/4321 FAMILY
RLNCF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
DS39689F-page 312
Q Cycle Activity:
Before Instruction
After Instruction
Decode
REG
REG
Q1
=
=
register ‘f’
Rotate Left f (No Carry)
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
(f<n>) → dest<n + 1>,
(f<7>) → dest<0>
N, Z
The contents of register ‘f’ are rotated
one bit to the left. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result is
stored back in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
1
1
RLNCF
RLNCF
Read
Q2
0100
1010 1011
0101 0111
f {,d {,a}}
01da
Process
REG, 1, 0
Data
register f
Q3
ffff
destination
Write to
Q4
ffff
RRCF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Decode
REG
C
REG
W
C
Q1
=
=
=
=
=
register ‘f’
Rotate Right f through Carry
RRCF
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
(f<n>) → dest<n – 1>,
(f<0>) → C,
(C) → dest<7>
C, N, Z
The contents of register ‘f’ are rotated
one bit to the right through the Carry
flag. If ‘d’ is ‘0’, the result is placed in W.
If ‘d’ is ‘1’, the result is placed back in
register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
1
1
RRCF
Read
0011
Q2
1110 0110
0
1110 0110
0111 0011
0
© 2009 Microchip Technology Inc.
C
f {,d {,a}}
00da
REG, 0, 0
Process
Data
Q3
register f
ffff
destination
Write to
Q4
ffff