PIC24FJ32GA102-I/SO Microchip Technology, PIC24FJ32GA102-I/SO Datasheet - Page 102
![IC MCU 16BIT 32KB FLASH 28SOIC](/photos/6/59/65909/150-28-soic_sml.jpg)
PIC24FJ32GA102-I/SO
Manufacturer Part Number
PIC24FJ32GA102-I/SO
Description
IC MCU 16BIT 32KB FLASH 28SOIC
Manufacturer
Microchip Technology
Series
PIC® XLP™ 24Fr
Datasheets
1.PIC24FJ32GA102-ISP.pdf
(308 pages)
2.PIC24FJ32GA102-ISP.pdf
(12 pages)
3.PIC24FJ32GA102-ISP.pdf
(48 pages)
4.PIC24FJ64GA104-IML.pdf
(300 pages)
Specifications of PIC24FJ32GA102-I/SO
Program Memory Type
FLASH
Program Memory Size
32KB (11K x 24)
Package / Case
28-SOIC (7.5mm Width)
Core Processor
PIC
Core Size
16-Bit
Speed
32MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
21
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC24FJ
Core
PIC
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
I2C/IrDA/SPI/UART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
21
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, DM240001, MA240020, DM240002, DM240011, DV164033
Minimum Operating Temperature
- 40 C
On-chip Adc
10-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
- PIC24FJ32GA102-ISP PDF datasheet
- PIC24FJ32GA102-ISP PDF datasheet #2
- PIC24FJ32GA102-ISP PDF datasheet #3
- PIC24FJ64GA104-IML PDF datasheet #4
- Current page: 102 of 308
- Download datasheet (3Mb)
PIC24FJ64GA104 FAMILY
8.1
The system clock source can be provided by one of
four sources:
• Primary Oscillator (POSC) on the OSCI and
• Secondary Oscillator (SOSC) on the SOSCI and
• Fast Internal RC (FRC) Oscillator
• Low-Power Internal RC (LPRC) Oscillator
The Primary Oscillator and FRC sources have the
option of using the internal 4x PLL. The frequency of
the FRC clock source can optionally be reduced by the
programmable clock divider. The selected clock source
generates the processor and peripheral clock sources.
The processor clock source is divided by two to pro-
duce the internal instruction cycle clock, F
document, the instruction cycle clock is also denoted
by F
can be provided on the OSCO I/O pin for some
operating modes of the Primary Oscillator.
TABLE 8-1:
DS39951C-page 102
Fast RC Oscillator with Postscaler
(FRCDIV)
(Reserved)
Low-Power RC Oscillator (LPRC)
Secondary (Timer1) Oscillator
(SOSC)
Primary Oscillator (XT) with PLL
Module (XTPLL)
Primary Oscillator (EC) with PLL
Module (ECPLL)
Primary Oscillator (HS)
Primary Oscillator (XT)
Primary Oscillator (EC)
Fast RC Oscillator with PLL Module
(FRCPLL)
Fast RC Oscillator (FRC)
Note 1:
OSCO pins
SOSCO pins
OSC
2:
/2. The internal instruction cycle clock, F
CPU Clocking Scheme
Oscillator Mode
OSCO pin function is determined by the OSCIOFCN Configuration bit.
This is the default oscillator mode for an unprogrammed (erased) device.
CONFIGURATION BIT VALUES FOR CLOCK SELECTION
Oscillator Source
CY
Secondary
Primary
Primary
Primary
Primary
Primary
. In this
Internal
Internal
Internal
Internal
Internal
OSC
/2,
8.2
The oscillator source (and operating mode) that is
used at a device Power-on Reset event is selected
using Configuration bit settings. The oscillator Config-
uration bit settings are located in the Configuration
registers
Section 25.1 “Configuration Bits” for further details).
The
POSCMD<1:0>
the Initial Oscillator Select Configuration bits,
FNOSC<2:0> (Configuration Word 2<10:8>), select
the oscillator source that is used at a Power-on Reset.
The FRC Primary Oscillator with postscaler (FRCDIV)
is the default (unprogrammed) selection. The Second-
ary Oscillator, or one of the internal oscillators, may be
chosen by programming these bit locations.
The Configuration bits allow users to choose between
the various clock modes, shown in Table 8-1.
8.2.1
The
Word 2<7:6>) are used to jointly configure device clock
switching and the Fail-Safe Clock Monitor (FSCM).
Clock switching is enabled only when FCKSM1 is
programmed (‘0’). The FSCM is enabled only when the
FCKSM<1:0> bits are both programmed (‘00’).
POSCMD<1:0>
FCKSM
Primary
11
xx
11
11
01
00
10
01
00
11
11
Initial Configuration on POR
in
CLOCK SWITCHING MODE
CONFIGURATION BITS
the
Configuration
(Configuration Word 2<1:0>), and
Oscillator
program
2010 Microchip Technology Inc.
FNOSC<2:0>
111
110
101
100
011
011
010
010
010
001
000
Configuration
memory
bits
(Configuration
(refer
Note
1, 2
1
1
1
1
1
bits,
to
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