ATMEGA328-PU Atmel, ATMEGA328-PU Datasheet - Page 209
![IC MCU AVR 32K FLASH 28PDIP](/photos/7/21/72189/453-28-dip_sml.jpg)
ATMEGA328-PU
Manufacturer Part Number
ATMEGA328-PU
Description
IC MCU AVR 32K FLASH 28PDIP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA328-PU
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Processor Series
ATMEGA328x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
2-Wire, SPI, USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
23
Number Of Timers
3
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 6 Channel
On-chip Dac
10 bit, 6 Channel
Operating Temperature Range
- 40 C to + 85 C
Processor To Be Evaluated
ATMEGA328
Supply Current (max)
0.2 mA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA328-PU
Manufacturer:
USB
Quantity:
3 200
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20.6
8271C–AVR–08/10
Data Transfer
Using the USART in MSPI mode requires the Transmitter to be enabled, i.e. the TXENn bit in
the UCSRnB register is set to one. When the Transmitter is enabled, the normal port operation
of the TxDn pin is overridden and given the function as the Transmitter's serial output. Enabling
the receiver is optional and is done by setting the RXENn bit in the UCSRnB register to one.
When the receiver is enabled, the normal pin operation of the RxDn pin is overridden and given
the function as the Receiver's serial input. The XCKn will in both cases be used as the transfer
clock.
After initialization the USART is ready for doing data transfers. A data transfer is initiated by writ-
ing to the UDRn I/O location. This is the case for both sending and receiving data since the
transmitter controls the transfer clock. The data written to UDRn is moved from the transmit buf-
fer to the shift register when the shift register is ready to send a new frame.
Note:
The following code examples show a simple USART in MSPIM mode transfer function based on
polling of the Data Register Empty (UDREn) Flag and the Receive Complete (RXCn) Flag. The
USART has to be initialized before the function can be used. For the assembly code, the data to
be sent is assumed to be stored in Register R16 and the data received will be available in the
same register (R16) after the function returns.
The function simply waits for the transmit buffer to be empty by checking the UDREn Flag,
before loading it with new data to be transmitted. The function then waits for data to be present
in the receive buffer by checking the RXCn Flag, before reading the buffer and returning the
value.
ATmega48A/48PA/88A/88PA/168A/168PA/328/328
To keep the input buffer in sync with the number of data bytes transmitted, the UDRn register must
be read once for each byte transmitted. The input buffer operation is identical to normal USART
mode, i.e. if an overflow occurs the character last received will be lost, not the first data in the buf-
fer. This means that if four bytes are transferred, byte 1 first, then byte 2, 3, and 4, and the UDRn
is not read before all transfers are completed, then byte 3 to be received will be lost, and not byte
1.
209
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