ATMEGA169P-16MCH Atmel, ATMEGA169P-16MCH Datasheet - Page 76

MCU AVR 16KB FLASH 16MHZ 64-VQFN

ATMEGA169P-16MCH

Manufacturer Part Number
ATMEGA169P-16MCH
Description
MCU AVR 16KB FLASH 16MHZ 64-VQFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet

Specifications of ATMEGA169P-16MCH

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
54
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32ATAVRBFLY - KIT EVALUATION AVR BUTTERFLYATSTK502 - MOD EXPANSION AVR STARTER 500ATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
8018P–AVR–08/10
low. When the SPI is enabled as a Master, the data direction of this pin is controlled by DDB0.
When the pin is forced to be an input, the pull-up can still be controlled by the PORTB0 bit.
PCINT8, Pin Change Interrupt Source 8: The PB0 pin can serve as an external interrupt source.
Table 13-7
signals shown in
tute the MISO signal, while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT.
Table 13-7.
Signal
Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
PTOE
DIEOE
DIEOV
DI
AIO
and
PB7/OC2A/
PCINT15
0
0
0
0
OC2A ENABLE
OC2A
PCINT15 • PCIE1
1
PCINT15 INPUT
Overriding Signals for Alternate Functions in PB7..PB4
Table 13-8 on page 77
Figure 13-5 on page
PB6/OC1B/
PCINT14
0
0
0
0
OC1B ENABLE
OC1B
PCINT14 • PCIE1
1
PCINT14 INPUT
71. SPI MSTR INPUT and SPI SLAVE OUTPUT consti-
relate the alternate functions of Port B to the overriding
PB5/OC1A/
PCINT13
0
0
0
0
OC1A ENABLE
OC1A
PCINT13 • PCIE1
1
PCINT13 INPUT
ATmega169P
PB4/OC0A/
PCINT12
0
0
0
0
OC0A ENABLE
OC0A
PCINT12 • PCIE1
1
PCINT12 INPUT
76

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