ATMEGA8535L-8PU Atmel, ATMEGA8535L-8PU Datasheet - Page 76
![IC AVR MCU 8K 8MHZ 3V 40DIP](/photos/6/70/67049/453-40-dip_sml.jpg)
ATMEGA8535L-8PU
Manufacturer Part Number
ATMEGA8535L-8PU
Description
IC AVR MCU 8K 8MHZ 3V 40DIP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA8535L-8PU
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Processor Series
ATMEGA8x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
2-Wire, SPI, USART
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
EWAVR, EWAVR-BL
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA8535L-8PU
Manufacturer:
TI
Quantity:
12 000
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Modes of Operation
Normal Mode
Clear Timer on Compare
Match (CTC) Mode
76
ATmega8535(L)
The mode of operation, i.e., the behavior of the Timer/Counter and the output compare
pins, is defined by the combination of the Waveform Generation mode (WGM01:0) and
Compare Output mode (COM01:0) bits. The Compare Output mode bits do not affect
the counting sequence, while the Waveform Generation mode bits do. The COM01:0
bits control whether the PWM output generated should be inverted or not (inverted or
non-inverted PWM). For non-PWM modes the COM01:0 bits control whether the output
should be set, cleared, or toggled at a Compare Match (See “Compare Match Output
Unit” on page 75.).
For detailed timing information refer to Figure 34, Figure 35, Figure 36, and Figure 37 in
“Timer/Counter Timing Diagrams” on page 80.
The simplest mode of operation is the Normal mode (WGM01:0 = 0). In this mode the
counting direction is always up (incrementing), and no counter clear is performed. The
counter simply overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then
restarts from the bottom (0x00). In normal operation the Timer/Counter Overflow Flag
(
Flag in this case behaves like a ninth bit, except that it is only set, not cleared. However,
combined with the Timer Overflow interrupt that automatically clears the TOV0 Flag, the
timer resolution can be increased by software. There are no special cases to consider in
the normal mode, a new counter value can be written anytime.
The output compare unit can be used to generate interrupts at some given time. Using
the output compare to generate waveforms in Normal mode is not recommended, since
this will occupy too much of the CPU time.
In Clear Timer on Compare or CTC mode (WGM01:0 = 2), the OCR0 Register is used to
manipulate the counter resolution. In CTC mode the counter is cleared to zero when the
counter value (TCNT0) matches the OCR0. The OCR0 defines the top value for the
counter, hence also its resolution. This mode allows greater control of the Compare
Match output frequency. It also simplifies the operation of counting external events.
The timing diagram for the CTC mode is shown in Figure 31. The counter value
(TCNT0) increases until a Compare Match occurs between TCNT0 and OCR0, and then
counter (TCNT0) is cleared.
Figure 31. CTC Mode, Timing Diagram
An interrupt can be generated each time the counter value reaches the TOP value by
using the OCF0 Flag. If the interrupt is enabled, the interrupt handler routine can be
used for updating the TOP value. However, changing TOP to a value close to BOTTOM
TOV
(Toggle)
TCNTn
Period
0) will be set in the same timer clock cycle as the TCNT0 becomes zero. The TOV0
OCn
1
2
3
4
OCn Interrupt Flag Set
(COMn1:0 = 1)
2502K–AVR–10/06
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