PIC16F871-I/PT Microchip Technology, PIC16F871-I/PT Datasheet - Page 99

• Manufacturer Part Number: PIC16F871-I/PT
• Description: IC MCU FLASH 2KX14 EE 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F871-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 3.5KB (2K x 14)
• Package / Case: 44-TQFP, 44-VQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 33
• Eeprom Size: 64 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: PSP, USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 33
• Number Of Timers: 8
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 28 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: I3-DB16F871 - BOARD DAUGHTER ICEPIC3
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

FIGURE 11-9:
11.10.1
External interrupt on the RB0/INT pin is edge triggered,
either rising, if bit INTEDG (OPTION_REG<6>) is set,
or falling, if the INTEDG bit is clear. When a valid edge
appears
(INTCON<1>) is set. This interrupt can be disabled by
clearing enable bit INTE (INTCON<4>). Flag bit INTF
must be cleared in software in the Interrupt Service
Routine before re-enabling this interrupt. The INT inter-
rupt can wake-up the processor from SLEEP, if bit INTE
was set prior to going into SLEEP. The status of global
interrupt enable bit, GIE, decides whether or not the
processor branches to the interrupt vector following
wake-up. See Section 11.13 for details on SLEEP
mode.
 2003 Microchip Technology Inc.
The following table shows which devices have which interrupts.
PIC18F870
PIC18F871
PSPIF
PSPIE
Device
EEIF
EEIE
on
INT INTERRUPT
TMR1IF
TMR1IE
ADIF
ADIE
the
T0IF
Yes
Yes
TMR2IF
TMR2IE
RB0/INT
RCIF
RCIE
INTERRUPT LOGIC
CCP1IF
CCP1IE
INTF
Yes
Yes
TXIF
TXIE
pin,
RBIF
Yes
Yes
flag
bit
PSPIF
Yes
—
INTF
ADIF
Yes
Yes
T0IF
T0IE
INTF
INTE
RBIF
RBIE
PEIE
GIE
RCIF
Yes
Yes
11.10.2
An overflow (FFh
flag bit T0IF (INTCON<2>). The interrupt can be
enabled/disabled by setting/clearing enable bit T0IE
(INTCON<5>) (Section 5.0).
11.10.3
An input change on PORTB<7:4> sets flag bit RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit RBIE (INTCON<4>)
(Section 4.2).
TXIF
Yes
Yes
TMR0 INTERRUPT
PORTB INTCON CHANGE
CCP1IF
PIC16F870/871
Yes
Yes
00h) in the TMR0 register will set
TMR2IF
Yes
Yes
Wake-up (If in SLEEP mode)
TMR1IF
Interrupt to CPU
DS30569B-page 97
Yes
Yes
EEIF
Yes
Yes