PIC18F4510-E/ML Microchip Technology, PIC18F4510-E/ML Datasheet - Page 287
![IC MCU FLASH 16KX16 44QFN](/photos/6/81/68122/150-44-qfn_sml.jpg)
PIC18F4510-E/ML
Manufacturer Part Number
PIC18F4510-E/ML
Description
IC MCU FLASH 16KX16 44QFN
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F2221-ISO.pdf
(46 pages)
3.PIC18LF2410-ISO.pdf
(376 pages)
4.PIC18LF2410-ISO.pdf
(8 pages)
5.PIC18LF2410-ISO.pdf
(16 pages)
6.PIC18LF2410-ISO.pdf
(6 pages)
7.PIC18LF2410-ISO.pdf
(6 pages)
8.PIC18LF2410-ISO.pdf
(8 pages)
Specifications of PIC18F4510-E/ML
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
36
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
44-QFN
For Use With
I3DB18F4620 - BOARD DAUGHTER ICEPIC3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
- PIC16F616T-ISL PDF datasheet
- PIC18F2221-ISO PDF datasheet #2
- PIC18LF2410-ISO PDF datasheet #3
- PIC18LF2410-ISO PDF datasheet #4
- PIC18LF2410-ISO PDF datasheet #5
- PIC18LF2410-ISO PDF datasheet #6
- PIC18LF2410-ISO PDF datasheet #7
- PIC18LF2410-ISO PDF datasheet #8
- Current page: 287 of 376
- Download datasheet (7Mb)
RCALL
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
© 2009 Microchip Technology Inc.
Q Cycle Activity:
Before Instruction
After Instruction
operation
Decode
No
PC =
PC =
TOS =
Q1
Read literal
Push PC to
Address (HERE)
Address (Jump)
Address (HERE + 2)
operation
Relative Call
RCALL
-1024 ≤ n ≤ 1023
(PC) + 2 → TOS,
(PC) + 2 + 2n → PC
None
Subroutine call with a jump up to 1K
from the current location. First, return
address (PC+2) is pushed onto the
stack. Then, add the 2’s complement
number ‘2n’ to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is a
two-cycle instruction.
1
2
HERE
stack
1101
No
Q2
‘n’
n
RCALL Jump
1nnn
operation
Process
Data
No
Q3
nnnn
Write to PC
operation
No
Q4
nnnn
RESET
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
After Instruction
PIC18F2X1X/4X1X
Decode
Registers =
Flags*
Q1
=
Reset
RESET
None
Reset all registers and flags that are
affected by a MCLR Reset.
All
This instruction provides a way to
execute a MCLR Reset in software.
1
1
RESET
Reset
Start
0000
Q2
Reset Value
Reset Value
0000
operation
No
Q3
DS39636D-page 289
1111
operation
No
Q4
1111
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