PIC18F2431-E/SP Microchip Technology, PIC18F2431-E/SP Datasheet - Page 272

• Manufacturer Part Number: PIC18F2431-E/SP
• Description: IC MCU FLASH 8KX16 28-DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2431-E/SP

• Core Size: 8-Bit
• Program Memory Size: 16KB (8K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, Power Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Controller Family/series: PIC18
• No. Of I/o's: 24
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 768Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: I3-DB18F4431 - BOARD DAUGHTER ICEPIC3AC164035 - MODULE SKT FOR 18F2X31 28SOICDVA18XP280 - DEVICE ADAPTER 18F2220 PDIP 28LD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC18F2331/2431/4331/4431
REGISTER 23-11: CONFIG7L: CONFIGURATION REGISTER 7 LOW (BYTE ADDRESS 30000Ch)
REGISTER 23-12: CONFIG7H: CONFIGURATION REGISTER 7 HIGH (BYTE ADDRESS 30000Dh)
DS39616D-page 272
bit 7
Legend:
R = Readable bit
-n = Value when device is unprogrammed
bit 7-4
bit 3
bit 2
bit 1
bit 0
Note 1:
bit 7
Legend:
R = Readable bit
-n = Value when device is unprogrammed
bit 7
bit 6
bit 5-0
Note 1:
U-0
U-0
—
—
2:
3:
2:
Unimplemented in PIC18F2331/4331 devices; maintain this bit set.
Refer to
Enabling the corresponding CPx bit is recommended to protect the block from external read operations.
Enabling the corresponding CPx bit is recommended to protect the block from external read operations.
Refer to
Unimplemented: Read as ‘0’
EBTR3: Table Read Protection bit
1 = Block 3 is not protected from table reads executed in other blocks
0 = Block 3 is protected from table reads executed in other blocks
EBTR2: Table Read Protection bit
1 = Block 2 is not protected from table reads executed in other blocks
0 = Block 2 is protected from table reads executed in other blocks
EBTR1: Table Read Protection bit
1 = Block 1 is not protected from table reads executed in other blocks
0 = Block 1 is protected from table reads executed in other blocks
EBTR0: Table Read Protection bit
1 = Block 0 is not protected from table reads executed in other blocks
0 = Block 0 is protected from table reads executed in other blocks
Unimplemented: Read as ‘0’
EBTRB: Boot Block Table Read Protection bit
1 = Boot block is not protected from table reads executed in other blocks
0 = Boot block is protected from table reads executed in other blocks
Unimplemented: Read as ‘0’
EBTRB
R/P-1
U-0
Figure 23-5
Figure 23-5
—
(1,2)
P = Programmable bit
P = Programmable bit
for block boundary addresses.
for block boundary addresses.
U-0
U-0
—
—
(1,2,3)
(1,2,3)
(2,3)
(2,3)
U-0
U-0
—
—
U = Unimplemented bit, read as ‘0’
U = Unchanged from programmed state
U = Unimplemented bit, read as ‘0’
U = Unchanged from programmed state
EBTR3
(1,2)
R/P-1
U-0
—
(1,2,3)
EBTR2
R/P-1
U-0
—
(1,2,3)
 2010 Microchip Technology Inc.
EBTR1
R/P-1
U-0
—
(2,3)
EBTR0
R/P-1
U-0
—
(2,3)
bit 0
bit 0