PIC24HJ16GP304-I/PT Microchip Technology, PIC24HJ16GP304-I/PT Datasheet - Page 53

IC PIC MCU FLASH 16K 44TQFP

PIC24HJ16GP304-I/PT

Manufacturer Part Number
PIC24HJ16GP304-I/PT
Description
IC PIC MCU FLASH 16K 44TQFP
Manufacturer
Microchip Technology
Series
PIC® 24Hr

Specifications of PIC24HJ16GP304-I/PT

Core Size
16-Bit
Program Memory Size
16KB (5.5K x 24)
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Core Processor
PIC
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Number Of I /o
35
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 13x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Controller Family/series
PIC24
No. Of I/o's
35
Ram Memory Size
2KB
Cpu Speed
40MIPS
No. Of Timers
4
Processor Series
PIC24HJ
Core
PIC
Data Bus Width
16 bit
Data Ram Size
2 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
35
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240001
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 13 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
876-1004 - PIC24 BREAKOUT BOARDDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC24HJ16GP304-I/PT
Manufacturer:
MICROCHIP
Quantity:
367
Part Number:
PIC24HJ16GP304-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
6.0
The Reset module combines all reset sources and
controls the device Master Reset Signal, SYSRST. The
following is a list of device Reset sources:
• POR: Power-on Reset
• BOR: Brown-out Reset
• MCLR: Master Clear Pin Reset
• SWR: RESET Instruction
• WDTO: Watchdog Timer Reset
• CM: Configuration Mismatch Reset
• TRAPR: Trap Conflict Reset
• IOPUWR: Illegal Condition Device Reset
FIGURE 6-1:
 2009 Microchip Technology Inc.
- Illegal Opcode Reset
- Uninitialized W Register Reset
- Security Reset
Note 1: This data sheet summarizes the features
2: Some registers and associated bits
RESETS
of
PIC24HJ16GP304 families of devices. It
is not intended to be a comprehensive
reference source. To complement the
information in this data sheet, refer to
“Section 8. Reset” (DS70192) of the
”dsPIC33F/PIC24H Family Reference
Manual”, which is available from the
Microchip website (www.microchip.com).
described in this section may not be avail-
able on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
PIC24HJ32GP202/204 and PIC24HJ16GP304
MCLR
the
V
DD
Uninitialized W Register
Configuration Mismatch
RESET SYSTEM BLOCK DIAGRAM
PIC24HJ32GP202/204
Regulator
RESET Instruction
Internal
Sleep or Idle
Illegal Opcode
Module
WDT
Trap Conflict
V
DD
Detect
Glitch Filter
Rise
and
Preliminary
BOR
POR
A simplified block diagram of the Reset module is
shown in Figure 6-1.
Any active source of reset will make the SYSRST
signal active. On system Reset, some of the registers
associated with the CPU and peripherals are forced to
a known Reset state and some are unaffected.
All types of device Reset sets a corresponding status
bit in the RCON register to indicate the type of Reset
(see Register 6-1).
A POR clears all the bits, except for the POR bit
(RCON<0>), that are set. The user application can set
or clear any bit at any time during code execution. The
RCON bits only serve as status bits. Setting a particular
Reset status bit in software does not cause a device
Reset to occur.
The RCON register also has other bits associated with
the Watchdog Timer and device power-saving states.
The function of these bits is discussed in other sections
of this manual.
Note:
Note:
Refer to the specific peripheral section or
Section 3.0 “CPU” of this manual for
register Reset states.
The status bits in the RCON register
should be cleared after they are read so
that the next RCON register value after a
device Reset is meaningful.
SYSRST
DS70289F-page 53

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