PIC18LF26J50-I/ML Microchip Technology, PIC18LF26J50-I/ML Datasheet - Page 4
![IC PIC MCU FLASH 64K 2V 28-QFN](/photos/6/81/68120/150-28-qfn_sml.jpg)
PIC18LF26J50-I/ML
Manufacturer Part Number
PIC18LF26J50-I/ML
Description
IC PIC MCU FLASH 64K 2V 28-QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18LF24J10-ISS.pdf
(32 pages)
2.PIC18LF24J50-ISS.pdf
(554 pages)
3.PIC18LF24J50-ISS.pdf
(12 pages)
Specifications of PIC18LF26J50-I/ML
Program Memory Type
FLASH
Program Memory Size
64KB (32K x 16)
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
16
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
4 KB
Interface Type
EUSART, I2C, SPI
Maximum Clock Frequency
31 KHz
Number Of Programmable I/os
16
Number Of Timers
5
Operating Supply Voltage
2 V to 3.6 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM183032, DV164136, MA180024, DM183022
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 10 Channel
A/d Bit Size
10 bit
A/d Channels Available
10
Height
0.88 mm
Length
6 mm
Supply Voltage (max)
2.75 V, 3.6 V
Supply Voltage (min)
2 V
Width
6 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18LF26J50-I/ML
Manufacturer:
MICROCHIP
Quantity:
4 000
PIC18F46J50 FAMILY
3. Module: Enhanced Universal
EXAMPLE 1:
DS80436C-page 4
;Initial conditions: SPEN = 0 (module disabled)
;To re-enable the module:
;Re-Initialize TXSTAx, BAUDCONx, SPBRGx, SPBRGHx registers (if needed)
;Re-Initialize RCSTAx register (if needed), but do not set SPEN = 1 yet
;Now enable the module, but add a 2-Tcy delay before executing any two-cycle
;instructions
bsf
nop
nop
;CPU may now execute 2 cycle instructions
In rare situations, when interrupts are enabled,
unexpected results may occur if:
• The EUSART is disabled (the SPEN bit,
• The EUSART is re-enabled (RCSTAx<7> = 1)
• A two-cycle instruction is executed immediately
Affected Silicon Revisions
A2
RCSTAx<7> = 0)
after setting SPEN = 1
X
RCSTA1, SPEN ;or RCSTA2 if EUSART2
;1 Tcy delay
;1 Tcy delay (two total)
A4
X
Synchronous Asynchronous
Receiver Transmitter (EUSART)
RE-ENABLING A EUSART MODULE
Work around
Add a 2 T
enables the EUSART module (sets SPEN = 1).
Refer to Example 1.
CY
delay after any instruction that re-
2010 Microchip Technology Inc.