PIC18F26J50-I/ML Microchip Technology, PIC18F26J50-I/ML Datasheet - Page 243
![IC PIC MCU FLASH 64K 2V 28-QFN](/photos/6/81/68120/150-28-qfn_sml.jpg)
PIC18F26J50-I/ML
Manufacturer Part Number
PIC18F26J50-I/ML
Description
IC PIC MCU FLASH 64K 2V 28-QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18LF24J10-ISS.pdf
(32 pages)
2.PIC18LF24J50-ISS.pdf
(554 pages)
3.PIC18LF24J50-ISS.pdf
(12 pages)
4.PIC18F26K20-ISO.pdf
(430 pages)
Specifications of PIC18F26J50-I/ML
Program Memory Type
FLASH
Program Memory Size
64KB (32K x 16)
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
16
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2.15 V ~ 3.6 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3776 B
Interface Type
EUSART, I2C, SPI
Maximum Clock Frequency
48 MHz
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM183032, DV164136, MA180024, DM183022
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 10 Channel
Package
28QFN EP
Device Core
PIC
Family Name
PIC18
Maximum Speed
48 MHz
Operating Supply Voltage
2.5|3.3 V
A/d Bit Size
10 bit
A/d Channels Available
10
Height
0.88 mm
Length
6 mm
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2.15 V
Width
6 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F26J50-I/ML
Manufacturer:
PANASONIC
Quantity:
2 000
- PIC18LF24J10-ISS PDF datasheet
- PIC18LF24J50-ISS PDF datasheet #2
- PIC18LF24J50-ISS PDF datasheet #3
- PIC18F26K20-ISO PDF datasheet #4
- Current page: 243 of 430
- Download datasheet (7Mb)
FIGURE 18-5:
TABLE 18-2:
© 2008 Microchip Technology Inc.
INTCON
PIR1
PIE1
IPR1
RCSTA
RCREG
TRISC
TXSTA
BAUDCON
SPBRGH
SPBRG
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
Note 1:
Name
Note:
RX/DT pin
Rcv Shift
Reg
Rcv Buffer Reg
Read Rcv
Buffer Reg
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
RCIDL
Reserved in PIC18F2XK20 devices; always maintain these bits clear.
This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.
EUSART Receive Register
EUSART Baud Rate Generator Register, High Byte
EUSART Baud Rate Generator Register, Low Byte
GIE/GIEH PEIE/GIEL
ABDOVF
PSPIF
PSPIE
PSPIP
TRISC7
CSRC
SPEN
Bit 7
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
(1)
(1)
(1)
Start
ASYNCHRONOUS RECEPTION
bit
bit 0
TRISC6
RCIDL
ADIF
ADIE
ADIP
Bit 6
RX9
TX9
bit 1
TMR0IE
TRISC5
DTRXP
SREN
TXEN
RCIF
RCIE
RCIP
Bit 5
bit 7/8
Preliminary
Stop
TRISC4
CKTXP
bit
INT0IE
CREN
SYNC
TXIE
TXIP
Bit 4
TXIF
Word 1
RCREG
Start
bit
bit 0
ADDEN
TRISC3
SENDB
BRG16
PIC18F2XK20/4XK20
SSPIE
SSPIP
SSPIF
RBIE
Bit 3
bit 7/8 Stop
TMR0IF
CCP1IF
CCP1IE
CCP1IP
TRISC2
Word 2
RCREG
BRGH
FERR
Bit 2
—
bit
Start
TMR2IF
TMR2IE
TMR2IP
TRISC1
INT0IF
OERR
TRMT
bit
WUE
Bit 1
TMR1IE
TMR1IP
TMR1IF
TRISC0
ABDEN
bit 7/8
RX9D
TX9D
RBIF
DS41303D-page 241
Bit 0
Stop
bit
on page
Values
Reset
59
59
60
59
59
59
57
60
60
60
59
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