ATMEGA16HVA-4CKU Atmel, ATMEGA16HVA-4CKU Datasheet - Page 59
ATMEGA16HVA-4CKU
Manufacturer Part Number
ATMEGA16HVA-4CKU
Description
MCU AVR 16K FLASH 4MHZ 36-LGA
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA16HVA-4CKU.pdf
(196 pages)
Specifications of ATMEGA16HVA-4CKU
Core Processor
AVR
Core Size
8-Bit
Speed
4MHz
Connectivity
SPI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
7
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 9 V
Data Converters
A/D 5x12b
Oscillator Type
External
Operating Temperature
-20°C ~ 85°C
Package / Case
36-LGA
Processor Series
ATMEGA16x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SPI
Maximum Clock Frequency
4 MHz
Number Of Programmable I/os
6
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRSB200, ATAVRSB201
Minimum Operating Temperature
- 20 C
On-chip Adc
12 bit, 5 Channel
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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14.2
14.3
14.3.1
14.3.2
8024A–AVR–04/08
High Voltage Ports as General Digital I/O
Overview
Configuring the Pin
Reading the Pin
The high voltage ports are high voltage tolerant open collector output ports. In addition they can
be used as general digital inputs.
pin, here generically called Pxn.
Figure 14-2. General High Voltage Digital I/O
Note:
Each port pin consist of two register bits: PORTxn and PINxn. As shown in
tion” on page
the PINx I/O address.
If PORTxn is written logic one, the port pin is driven low (zero). If PORTxn is written logic zero,
the port pin is tri-stated. The port pins are tri-stated when a reset condition becomes active, even
if no clocks are running.
The port pin can be read through the PINxn Register bit. As shown in
Register bit and the preceding latch constitute a synchronizer. This is needed to avoid metasta-
bility if the physical pin changes value near the edge of the internal clock, but it also introduces a
delay.
1. WRx, RRx and RPx are common to all pins within the same port. clk
mon to all ports.
Pxn
62, the PORTxn bits are accesed at the PORTx I/O address, and the PINxn bits at
SLEEP:
clkI/O:
SLEEP CONTROL
I/O CLOCK
Figure 14-2
SLEEP
shows a functional description of one output port
(1)
SYNCHRONIZER
RRx:
WRx:
RPx:
D
L
ATmega8HVA/16HVA
RESET
CLR
SET
PORTxn
Q
Q
_
CLR
Q
_
Q
READ PORTx REGISTER
WRITE PORTx REGISTER
READ PINx REGISTER
D
D
PINxn
CLR
Q
_
Q
RRx
WRx
clk
RPx
Figure
I/O
I/O
and SLEEP are com-
”Register Descrip-
14-2, the PINxn
59
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