ATMEGA16HVA-4TU Atmel, ATMEGA16HVA-4TU Datasheet - Page 78
ATMEGA16HVA-4TU
Manufacturer Part Number
ATMEGA16HVA-4TU
Description
MCU AVR 16K FLASH 4MHZ 28-TSOP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA16HVA-4CKU.pdf
(196 pages)
Specifications of ATMEGA16HVA-4TU
Core Processor
AVR
Core Size
8-Bit
Speed
4MHz
Connectivity
SPI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
7
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 9 V
Data Converters
A/D 5x12b
Oscillator Type
External
Operating Temperature
-20°C ~ 85°C
Package / Case
28-TSOP
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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17.2.1
17.2.2
17.3
78
Timer/Counter Clock Sources
ATmega8HVA/16HVA
Registers
Definitions
The Timer/Counter Low Byte Register (TCNTnL) and Output Compare Registers (OCRnA and
OCRnB) are 8-bit registers. Interrupt request (abbreviated to Int.Req. in
signals are all visible in the Timer Interrupt Flag Register (TIFRn). All interrupts are individually
masked with the Timer Interrupt Mask Register (TIMSKn). TIFRn and TIMSKn are not shown in
the figure.
In 16-bit mode the Timer/Counter consists one more 8-bit register, the Timer/Counter High Byte
Register (TCNTnH). Furthermore, there is only one Output Compare Unit in 16-bit mode as the
two Output Compare Registers, OCRnA and OCRnB, are combined to one 16-bit Output Com-
pare Register. OCRnA contains the low byte of the word and OCRnB contains the higher byte of
the word. When accessing 16-bit registers, special procedures described in section
Registers in 16-bit Mode” on page 86
The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on
the Tn pin. The Clock Select logic block controls which clock source and edge the Timer/Counter
uses to increment its value. The Timer/Counter is inactive when no clock source is selected. The
output from the Clock Select logic is referred to as the timer clock (clk
Many register and bit references in this section are written in general form. A lower case “n”
replaces the module number, e.g. Timer/Counter number. A lower case “x” replaces the unit,
e.g. OCRnx and ICPnx describes OCRnB/A and ICP1/0x . However, when using the register or
bit defines in a program, the precise form must be used, i.e., TCNT0L for accessing
Timer/Counter0 counter value and so on.
The definitions in
Table 17-1.
The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source.
The Clock Select logic is controlled by the Clock Select (CSn2:0) bits located in the
Timer/Counter Control Register n B (TCCRnB), and controls which clock source and edge the
Timer/Counter uses to increment its value. The Timer/Counter is inactive when no clock source
is selected. The output from the Clock Select logic is referred to as the timer clock (clk
details on clock sources and prescaler, see
page 74
BOTTOM
MAX
TOP
The counter reaches the BOTTOM when it becomes 0.
The counter reaches its MAXimum when it becomes 0xFF (decimal 255) in 8-bit mode or
0xFFFF (decimal 65535) in 16-bit mode.
The counter reaches the TOP when it becomes equal to the highest value in the count
sequence. The TOP value can be assigned to be the fixed value 0xFF/0xFFFF (MAX) or
the value stored in the OCRnA Register.
Definitions
Table 17-1
are also used extensively throughout the document.
must be followed.
”Timer/Counter0 and Timer/Counter1 Prescalers” on
Tn
).
Figure 17-1 on page
8024A–AVR–04/08
”Accessing
Tn
). For
77)
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