PIC16C711-20I/SO Microchip Technology, PIC16C711-20I/SO Datasheet - Page 14

• Manufacturer Part Number: PIC16C711-20I/SO
• Description: IC MCU OTP 1KX14 A/D 18SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C711-20I/SO

• Program Memory Type: OTP
• Program Memory Size: 1.75KB (1K x 14)
• Package / Case: 18-SOIC (7.5mm Width)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 13
• Ram Size: 68 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Data Converters: A/D 4x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC16C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 68 B
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 13
• Number Of Timers: 1
• Operating Supply Voltage: 2.5 V to 6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 4-ch x 8-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT18SO-1 - SOCKET TRANSITION 18SOIC 300MILISPICR1 - ADAPTER IN-CIRCUIT PROGRAMMING309-1011 - ADAPTER 18-SOIC TO 18-DIP309-1010 - ADAPTER 18-SOIC TO 18-DIPAC164010 - MODULE SKT PROMATEII DIP/SOIC
• Eeprom Size: -
• Connectivity: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC16C71X
4.2.2
The Special Function Registers are registers used by
the CPU and Peripheral Modules for controlling the
desired operation of the device. These registers are
implemented as static RAM.
TABLE 4-1:
DS30272A-page 14
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'.
Note 1: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
Address Name
Bank 0
Bank 1
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(4)
(3)
(2,3)
(3)
(2,3)
(3)
2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose
3: These registers can be addressed from either bank.
4: The PCON register is not physically implemented in the PIC16C71, read as ’0’.
5: The IRP and RP1 bits are reserved on the PIC16C710/71/711, always maintain these bits clear.
6: Bit5 of ADCON0 is a General Purpose R/W bit for the PIC16C710/711 only. For the PIC16C71, this bit is unimplemented,
INDF
TMR0
PCL
STATUS
FSR
PORTA
PORTB
ADCON0
ADRES
PCLATH
INTCON
INDF
OPTION
PCL
STATUS
FSR
TRISA
TRISB
PCON
ADCON1
ADRES
PCLATH
INTCON
SPECIAL FUNCTION REGISTERS
Shaded locations are unimplemented, read as ‘0’.
contents are transferred to the upper byte of the program counter.
read as '0'.
—
PIC16C710/71/711 SPECIAL FUNCTION REGISTER SUMMARY
Addressing this location uses contents of FSR to address data memory (not a physical register)
Timer0 module’s register
Program Counter's (PC) Least Significant Byte
Indirect data memory address pointer
PORTB Data Latch when written: PORTB pins when read
Unimplemented
A/D Result Register
Addressing this location uses contents of FSR to address data memory (not a physical register)
Program Counter's (PC) Least Significant Byte
Indirect data memory address pointer
PORTB Data Direction Control Register
A/D Result Register
ADCS1
RBPU
IRP
IRP
Bit 7
GIE
GIE
—
—
—
—
—
—
(5)
(5)
INTEDG
ADCS0
RP1
RP1
ADIE
ADIE
Bit 6
—
—
—
—
—
—
(5)
(5)
T0CS
Bit 5
T0IE
T0IE
RP0
RP0
(6)
—
—
—
—
—
—
PORTA Data Latch when written: PORTA pins when read
Write Buffer for the upper 5 bits of the Program Counter
PORTA Data Direction Register
Write Buffer for the upper 5 bits of the Program Counter
CHS1
T0SE
INTE
INTE
Bit 4
TO
TO
—
—
CHS0
RBIE
RBIE
Bit 3
PSA
PD
PD
—
—
The special function registers can be classified into two
sets (core and peripheral). Those registers associated
with the “core” functions are described in this section,
and those related to the operation of the peripheral fea-
tures are described in the section of that peripheral
feature.
GO/DONE
Bit 2
T0IF
T0IF
PS2
—
—
Z
Z
PCFG1
ADIF
INTF
POR
INTF
Bit 1
PS1
DC
DC
PCFG0
ADON
1997 Microchip Technology Inc.
RBIF
BOR
RBIF
Bit 0
PS0
C
C
0000 0000 0000 0000
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
0001 1xxx 000q quuu
xxxx xxxx uuuu uuuu
---x 0000 ---u 0000
xxxx xxxx uuuu uuuu
00-0 0000 00-0 0000
xxxx xxxx uuuu uuuu
---0 0000 ---0 0000
0000 000x 0000 000u
0000 0000 0000 0000
1111 1111 1111 1111
0000 0000 0000 0000
0001 1xxx 000q quuu
xxxx xxxx uuuu uuuu
---1 1111 ---1 1111
1111 1111 1111 1111
---- --qq ---- --uu
---- --00 ---- --00
xxxx xxxx uuuu uuuu
---0 0000 ---0 0000
0000 000x
Value on:
POR,
BOR
—
other resets
Value on all
0000 000u
(1)
—