PIC18F65K90-I/PTRSL Microchip Technology, PIC18F65K90-I/PTRSL Datasheet - Page 192
![MCU PIC 32K FLASH MEM XLP 64TQFP](/photos/6/81/68123/c04-066_pf_sml.jpg)
PIC18F65K90-I/PTRSL
Manufacturer Part Number
PIC18F65K90-I/PTRSL
Description
MCU PIC 32K FLASH MEM XLP 64TQFP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Specifications of PIC18F65K90-I/PTRSL
Core Size
8-Bit
Program Memory Size
32KB (16K x 16)
Core Processor
PIC
Speed
64MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
53
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TFQFP
Controller Family/series
PIC18
Eeprom Memory Size
1024Byte
Ram Memory Size
2048Byte
Cpu Speed
16MIPS
No. Of Timers
8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F65K90-I/PTRSL
Manufacturer:
Microchip Technology
Quantity:
10 000
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PIC18F87K90 FAMILY
FIGURE 13-4:
13.8.2
The Timer1 gate source can be selected from one of
four sources. Source selection is controlled by the
T1GSSx bits, T1GCON<1:0> (see Table 13-4).
TABLE 13-4:
The polarity for each available source is also selectable,
controlled by the T1GPOL bit (T1GCON<6>).
13.8.2.1
The T1G pin is one source for Timer1 gate control. It
can be used to supply an external source to the Timer1
gate circuitry.
DS39957B-page 192
T1GSS<1:0>
00
01
10
11
TMR1GE
T1GPOL
T1GVAL
T1G_IN
Timer1
T1CKI
TIMER1 GATE SOURCE
SELECTION
T1G Pin Gate Operation
Timer1 Gate Pin
TMR2 to Match PR2
(TMR2 increments to match PR2)
Comparator 1 Output
(Comparator logic high output)
Comparator 2 Output
(Comparator logic high output)
TIMER1 GATE SOURCES
TIMER1 GATE COUNT ENABLE MODE
Timer1 Gate Source
N
Preliminary
N + 1
13.8.2.2
The TMR2 register will increment until it matches the
value in the PR2 register. On the very next increment
cycle, TMR2 will be reset to 00h. When this Reset
occurs, a low-to-high pulse will automatically be gener-
ated and internally supplied to the Timer1 gate circuitry.
The pulse will remain high for one instruction cycle and
will return back to a low state until the next match.
Depending on T1GPOL, Timer1 increments differently
when TMR2 matches PR2. When T1GPOL = 1, Timer1
increments for a single instruction cycle following a
TMR2 match with PR2. When T1GPOL = 0, Timer1
increments continuously, except for the cycle following
the match, when the gate signal goes from low-to-high.
13.8.2.3
The output of Comparator 1 can be internally supplied
to the Timer1 gate circuitry. After setting up
Comparator 1 with the CM1CON register, Timer1 will
increment depending on the transition of the
CMP1OUT (CMSTAT<5>) bit.
13.8.2.4
The output of Comparator 2 can be internally supplied
to the Timer1 gate circuitry. After setting up
Comparator 2 with the CM2CON register, Timer1 will
increment depending on the transition of the
CMP2OUT (CMSTAT<6>) bit.
N + 2
Timer2 Match Gate Operation
Comparator 1 Output Gate Operation
Comparator 2 Output Gate Operation
2010 Microchip Technology Inc.
N + 3
N + 4
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