PIC18F65K90-I/PTRSL Microchip Technology, PIC18F65K90-I/PTRSL Datasheet - Page 206
PIC18F65K90-I/PTRSL
Manufacturer Part Number
PIC18F65K90-I/PTRSL
Description
MCU PIC 32K FLASH MEM XLP 64TQFP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Specifications of PIC18F65K90-I/PTRSL
Core Size
8-Bit
Program Memory Size
32KB (16K x 16)
Core Processor
PIC
Speed
64MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
53
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TFQFP
Controller Family/series
PIC18
Eeprom Memory Size
1024Byte
Ram Memory Size
2048Byte
Cpu Speed
16MIPS
No. Of Timers
8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F65K90-I/PTRSL
Manufacturer:
Microchip Technology
Quantity:
10 000
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PIC18F87K90 FAMILY
15.5.4
When Timer3/5/7 Gate Single Pulse mode is enabled,
it is possible to capture a single pulse gate event.
Timer3/5/7 Gate Single Pulse mode is first enabled by
setting the TxGSPM bit (TxGCON<4>). Next, the
TxGGO/TxDONE bit (TxGCON<3>) must be set.
The Timer3/5/7 will be fully enabled on the next incre-
menting edge. On the next trailing edge of the pulse,
the TxGGO/TxDONE bit will automatically be cleared.
FIGURE 15-4:
DS39957B-page 206
Timer3/5/7
TMRxGIF
TMRxGE
TxGSPM
TxDONE
TxGPOL
TxGGO/
TxGVAL
TxG_IN
T1CKI
TIMER3/5/7 GATE SINGLE PULSE
MODE
TIMER3/5/7 GATE SINGLE PULSE MODE
Cleared by Software
N
Counting Enabled on
Set by Software
Rising Edge of TxG
Preliminary
N + 1
No other gate events will be allowed to increment
Timer3/5/7 until the TxGGO/TxDONE bit is once again
set in software.
Clearing the TxGSPM bit also will clear the TxGGO/
TxDONE bit. (For timing details, see Figure 15-4.)
Simultaneously enabling the Toggle mode and the
Single Pulse mode will permit both sections to work
together. This allows the cycle times on the Timer3/5/7
gate source to be measured. (For timing details, see
Figure 15-5.)
Set by Hardware on
Falling Edge of TxGVAL
Cleared by Hardware on
Falling Edge of TxGVAL
N + 2
2010 Microchip Technology Inc.
Software
Cleared by
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