PIC16C925-I/L Microchip Technology, PIC16C925-I/L Datasheet - Page 158

• Manufacturer Part Number: PIC16C925-I/L
• Description: IC MCU OTP 4KX14 LCD DVR 68PLCC
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C925-I/L

• Core Size: 8-Bit
• Program Memory Size: 7KB (4K x 14)
• Core Processor: PIC
• Speed: 20MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Type: OTP
• Ram Size: 176 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 68-PLCC
• Controller Family/series: PIC16C
• No. Of I/o's: 25
• Ram Memory Size: 176Byte
• Cpu Speed: 20MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 1
• Rohs Compliant: Yes
• Embedded Interface Type: I2C, SPI
• Processor Series: PIC16C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 176 B
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 1 x 16 bit
• Operating Supply Voltage: 2.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 5 bit
• Data Rom Size: 176 B
• Height: 4.06 mm
• Length: 24.33 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4 V
• Width: 24.33 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164308 - MODULE SKT FOR PM3 68PLCCDVA16XL680 - ADAPTER DEVICE FOR MPLAB-ICEAC164024 - ADAPTER PICSTART PLUS 68PLCCAC164022 - MODULE SKT PROMATEII 68PLCC
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC16C925I/L

PIC16C925/926
FIGURE 15-15:
TABLE 15-10: I
DS39544A-page 156
100
101
102
103
90
91
106
107
92
109
110
D102
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
Parameter
No.
Note:
SDA
Out
SDA
In
SCL
(min. 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
T
T
T
T
T
T
T
T
T
T
T
C
Symbol
SU
SU
SU
AA
HIGH
LOW
R
F
HD
HD
BUF
B
:
:
:
:
:
STA
DAT
STO
Refer to Figure 15-4 for load conditions.
STA
DAT
2
C BUS DATA REQUIREMENTS
I
2
90
C BUS DATA TIMING
Clock high time
Clock low time
SDA and SCL rise
time
SDA and SCL fall
time
START condition
setup time
START condition
hold time
Data input hold
time
Data input setup
time
STOP condition
setup time
Output valid from
clock
Bus free time
Bus capacitive loading
103
91
109
Characteristic
100 kHz mode
SSP Module
100 kHz mode
SSP Module
100 kHz mode
100 kHz mode
100 kHz mode
100 kHz mode
100 kHz mode
100 kHz mode
100 kHz mode
100 kHz mode
100 kHz mode
100
Preliminary
106
101
109
1.5T
1.5T
Min
250
4.0
4.7
4.7
4.0
4.7
4.7
—
—
—
—
0
107
CY
CY
1000
3500
Max
300
400
—
—
—
—
—
—
—
—
—
—
Units
pF
ns
ns
ns
ns
ns
s
s
s
s
s
s
2001 Microchip Technology Inc.
92
Device must operate at a
minimum of 1.5 MHz
Device must operate at a
minimum of 1.5 MHz
Only relevant for Repeated
START condition
After this period the first
clock pulse is generated
(Note 1)
Time the bus must be free
before a new transmission
can start
102
110
Conditions