AT32UC3L064-D3HR Atmel, AT32UC3L064-D3HR Datasheet - Page 63

• Manufacturer Part Number: AT32UC3L064-D3HR
• Description: MCU AVR32 64K FLASH 48TTLGA
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3L064-D3HR

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 3.6 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

7.10
7.10.1
Table 7-36.
Note:
7.10.2
Table 7-37.
Note:
32099F–11/2010
Parameter
Startup time from power-up, using
regulator
Startup time from power-up, no
regulator
Startup time from reset release
Wake-up
Wake-up from shutdown
Symbol
t
RESET
Timing Characteristics
1. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro-
1. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro-
Startup, Reset, and Wake-up Timing
RESET_N Timing
cess technology. These values are not covered by test limits in production.
cess technology. These values are not covered by test limits in production.
Maximum Reset and Wake-up Timing
RESET_N Waveform Parameters
Parameter
RESET_N minimum pulse length
Idle
Frozen
Standby
Stop
Deepstop
Static
The startup, reset, and wake-up timings are calculated using the following formula:
Where
another clock source than RCSYS is selected as CPU clock the startup time of the oscillator,
Please refer to the source for the CPU clock in the
more details about oscillator startup times.
t
t
OSCSTART
=
t
CONST
t
CONST
Time from VDDIN crossing the V
POR33 to the first instruction entering the decode
stage of CPU. VDDCORE is supplied by the internal
regulator.
Time from VDDIN crossing the V
POR33 to the first instruction entering the decode
stage of CPU. VDDCORE is connected to VDDIN.
Time from releasing a reset source (except POR18,
POR33, and SM33) to the first instruction entering
the decode stage of CPU.
From wake-up event to the first instruction of an
interrupt routine entering the decode stage of the
CPU.
From wake-up event to the first instruction entering
the decode stage of the CPU.
Measuring
, must added to the wake-up time in the stop, deepstop, and static sleep modes.
+
N
and
CPU
×
N
(1)
CPU
t
CPU
(1)
are found in
Conditions
POT+
POT+
Table
threshold of
threshold of
7-36.
”Oscillator Characteristics” on page 50
t
CPU
AT32UC3L016/32/64
Min
10
Max
is the period of the CPU clock. If
27 +
27 +
97 +
t
CONST
t
t
t
2210
1810
1180
OSCSTART
OSCSTART
OSCSTART
170
0
0
0
Max
(in µs)
Units
ns
Max
110
110
116
116
116
N
19
0
0
0
0
CPU
for
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