AT32UC3B064-Z2UR Atmel, AT32UC3B064-Z2UR Datasheet - Page 285
![MCU AVR32 64K FLASH 64-QFN](/photos/12/13/121326/313-64-qfn_sml.jpg)
AT32UC3B064-Z2UR
Manufacturer Part Number
AT32UC3B064-Z2UR
Description
MCU AVR32 64K FLASH 64-QFN
Manufacturer
Atmel
Series
AVR®32 UC3r
Datasheet
1.AT32UC3B164-AUR.pdf
(680 pages)
Specifications of AT32UC3B064-Z2UR
Package / Case
64-QFN
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Operating Temperature
-40°C ~ 85°C
Speed
60MHz
Number Of I /o
44
Core Processor
AVR
Program Memory Type
FLASH
Ram Size
16K x 8
Program Memory Size
64KB (64K x 8)
Data Converters
A/D 8x10b
Oscillator Type
Internal
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Connectivity
I²C, IrDA, SPI, SSC, UART/USART, USB
Core Size
32-Bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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20.9.5
Name:
Access Type:
Offset:
Reset value:
• PERIOD: Transmit Period Divider Selection
• STTDLY: Transmit Start Delay
• START: Transmit Start Selection
32059J–12/2010
31
23
15
7
-
START
Others
This field selects the divider to apply to the selected transmit clock in order to generate a periodic Frame Sync Signal.
If equal to zero, no signal is generated.
If not equal to zero, a signal is generated each 2 x (PERIOD+1) transmit clock periods.
If STTDLY is not zero, a delay of STTDLY clock cycles is inserted between the start event and the actual start of transmission.
When the transmitter is programmed to start synchronously with the receiver, the delay is also applied.
Note: STTDLY must be written carefully, in relation to Transmit Sync Data transmission.
0
1
2
3
4
5
6
7
Transmit Clock Mode Register
CKG
30
22
14
6
-
TCMR
Read/Write
0x18
0x00000000
Transmit Start
Continuous, as soon as a word is written to the THR Register (if Transmit is enabled), and
immediately after the end of transfer of the previous data.
Receive start
Detection of a low level on TX_FRAME_SYNC signal
Detection of a high level on TX_FRAME_SYNC signal
Detection of a falling edge on TX_FRAME_SYNC signal
Detection of a rising edge on TX_FRAME_SYNC signal
Detection of any level change on TX_FRAME_SYNC signal
Detection of any edge on TX_FRAME_SYNC signal
Reserved
CKI
29
21
13
5
-
28
20
12
4
-
PERIOD
STTDLY
CKO
27
19
11
3
26
18
10
2
START
25
17
9
1
AT32UC3B
CKS
24
16
8
0
285
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