PIC16C72-20/SP Microchip Technology, PIC16C72-20/SP Datasheet - Page 50

• Manufacturer Part Number: PIC16C72-20/SP
• Description: IC MCU OTP 2KX14 A/D PWM 28DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C72-20/SP

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: OTP
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Data Converters: A/D 5x8b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Processor Series: PIC16C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: I2C, SPI, SSP
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 1 x 16 bit
• Operating Supply Voltage: 2.5 V to 6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000, DM163022
• Minimum Operating Temperature: 0 C
• On-chip Adc: 5 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: Q858228

PIC16C72 Series
8.4.1.3
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the
SSPSTAT register is set. The received address is
loaded into the SSPBUF register. The ACK pulse will
be sent on the ninth bit, and pin RC3/SCK/SCL is held
low. The transmit data must be loaded into the SSP-
BUF register, which also loads the SSPSR register.
Then pin RC3/SCK/SCL should be enabled by setting
bit CKP (SSPCON<4>). The master must monitor the
SCL pin prior to asserting another clock pulse. The
slave devices may be holding off the master by stretch-
ing the clock. The eight data bits are shifted out on the
falling edge of the SCL input. This ensures that the SDA
signal is valid during the SCL high time (Figure 8-9).
FIGURE 8-9:
DS39016A-page 50
SDA
SCL
SSPIF (PIR1<3>)
BF (SSPSTAT<0>)
CKP (SSPCON<4>)
S
TRANSMISSION
A7
1
Data in
sampled
I
2
C WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)
A6
2
A5
Receiving Address
3
A4
4
A3
5
A2
6
A1
7
R/W = 1
8
Preliminary
9
ACK
responds to SSPIF
SCL held low
while CPU
An SSP interrupt is generated for each data transfer
byte. Flag bit SSPIF must be cleared in software, and
the SSPSTAT register is used to determine the status
of the byte. Flag bit SSPIF is set on the falling edge of
the ninth clock pulse.
As a slave-transmitter, the ACK pulse from the master-
receiver is latched on the rising edge of the ninth SCL
input pulse. If the SDA line was high (not ACK), then the
data transfer is complete. When the ACK is latched by
the slave, the slave logic is reset (resets SSPSTAT reg-
ister) and the slave then monitors for another occur-
rence of the START bit. If the SDA line was low (ACK),
the transmit data must be loaded into the SSPBUF reg-
ister, which also loads the SSPSR register. Then pin
RC3/SCK/SCL should be enabled by setting bit CKP.
D7
1
SSPBUF is written in software
D6
2
cleared in software
Set bit after writing to SSPBUF
(the SSPBUF must be written-to
before the CKP bit can be set)
D5
3
D4
4
Transmitting Data
D3
5
1998 Microchip Technology Inc.
D2
6
From SSP interrupt
service routine
D1
7
D0
8
ACK
9
P