ATMEGA3290P-20AUR Atmel, ATMEGA3290P-20AUR Datasheet - Page 312
ATMEGA3290P-20AUR
Manufacturer Part Number
ATMEGA3290P-20AUR
Description
MCU AVR 32K FLASH 20MHZ 64TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA3290P-20AUR
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
69
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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27.7.16
27.7.17
8021G–AVR–03/11
Serial Programming Pin Mapping
Serial Programming Algorithm
Table 27-16. Pin Mapping Serial Programming
Figure 27-10. Serial Programming and Verify
Notes:
When programming the EEPROM, an auto-erase cycle is built into the self-timed programming
operation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase
instruction. The Chip Erase operation turns the content of every memory location in both the
Program and EEPROM arrays into 0xFF.
Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods
for the serial clock (SCK) input are defined as follows:
Low: > 2 CPU clock cycles for f
High: > 2 CPU clock cycles for f
When writing serial data to the ATmega329P/3290P, data is clocked on the rising edge of SCK.
When reading data from the ATmega329P/3290P, data is clocked on the falling edge of SCK.
See
To program and verify the ATmega329P/3290P in the serial programming mode, the following
sequence is recommended (See four byte instruction formats in
1. Power-up sequence:
Apply power between V
Figure 27-11
1. If the device is clocked by the internal Oscillator, it is no need to connect a clock source to the
2. V
Symbol
MOSI
MISO
SCK
XTAL1 pin.
CC
- 0.3V < AVCC < V
for timing details.
CC
and GND while RESET and SCK are set to “0”. In some sys-
Pins
PB2
PB3
PB1
ck
ck
CC
MOSI
MISO
< 12MHz, 3 CPU clock cycles for f
< 12MHz, 3 CPU clock cycles for f
SCK
+ 0.3V, however, AVCC should always be within 1.8 - 5.5V
XTAL1
RESET
GND
(1)
I/O
O
I
I
AVCC
VCC
+1.8 - 5.5V
+1.8 - 5.5V
ATmega329P/3290P
(2)
Table
ck
ck
Serial Data out
Serial Data in
Description
27-18):
Serial Clock
>= 12MHz
>= 12MHz
312
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