PIC16C773-I/SS Microchip Technology, PIC16C773-I/SS Datasheet - Page 109

• Manufacturer Part Number: PIC16C773-I/SS
• Description: IC MCU OTP 4KX14 A/D PWM 28SSOP
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C773-I/SS

• Program Memory Type: OTP
• Program Memory Size: 7KB (4K x 14)
• Package / Case: 28-SSOP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC16C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C/SPI/SSP/UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 3
• Operating Supply Voltage: 2.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000, DM163022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 6-ch x 12-bit
• Controller Family/series: PIC16C
• No. Of I/o's: 22
• Ram Memory Size: 256Byte
• Cpu Speed: 20MHz
• No. Of Timers: 3
• Embedded Interface Type: I2C, SPI, USART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 309-1025 - ADAPTER 28-SSOP TO 28-DIP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

9.3.2
Once Synchronous mode is selected, reception is
enabled by setting either enable bit SREN (RCSTA<5>)
or enable bit CREN (RCSTA<4>). Data is sampled on
the RC7/RX/DT pin on the falling edge of the clock. If
enable bit SREN is set, then only a single word is
received. If enable bit CREN is set, the reception is
continuous until CREN is cleared. If both bits are set
then CREN takes precedence.
Steps to follow when setting up a Synchronous Master
Reception:
1.
2.
TABLE 9-9
FIGURE 9-11: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
Address Name
0Ch
18h
1Ah
8Ch
98h
99h
Legend: x = unknown, - = unimplemented read as '0'. Shaded cells are not used for Synchronous Master Reception.
Note 1: Bits PSPIE and PSPIF are reserved on the 28-pin devices, always maintain these bits clear.
1999 Microchip Technology Inc.
RC7/RX/DT pin
RC6/TX/CK pin
Initialize the SPBRG register for the appropriate
baud rate.
Enable the synchronous master serial port by
setting bits SYNC, SPEN, and CSRC.
USART SYNCHRONOUS MASTER
RECEPTION
Write to
bit SREN
SREN bit
CREN bit
RCIF bit
(interrupt)
Read
RXREG
PIR1
RCSTA
RCREG USART Receive Register
PIE1
TXSTA
SPBRG Baud Rate Generator Register
(Section
Q2
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
'0'
Note: Timing diagram demonstrates SYNC master mode with bit SREN = '1' and bit BRGH = '0'.
PSPIF
PSPIE
SPEN
CSRC
Bit 7
9.1)
(1)
(1)
ADIE
ADIF
Bit 6
RX9
TX9
bit0
SREN CREN ADDEN
TXEN SYNC
RCIF
RCIE
Bit 5
Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
bit1
Advance Information
TXIE
Bit 4
TXIF
bit2
SSPIE
SSPIF
Bit 3
—
CCP1IF TMR2IF TMR1IF
CCP1IE TMR2IE TMR1IE
bit3
BRGH
FERR
Bit 2
3.
4.
5.
6.
7.
8.
9.
10. If any error occurred, clear the error by clearing
Ensure bits CREN and SREN are clear.
If interrupts are desired, then set enable bit
RCIE.
If 9-bit reception is desired, then set bit RX9.
If a single reception is required, set bit SREN.
For continuous reception set bit CREN.
Interrupt flag bit RCIF will be set when reception
is complete and an interrupt will be generated if
enable bit RCIE was set.
Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
Read the 8-bit received data by reading the
RCREG register.
bit CREN.
bit4
OERR
TRMT
Bit 1
bit5
RX9D
TX9D
Bit 0
bit6
PIC16C77X
0000 0000
0000 0000
0000 -010
0000 0000
0000 000x
0000 0000
Value on:
POR,
BOR
bit7
DS30275A-page 109
other Resets
Value on all
0000 0000
0000 000x
0000 0000
0000 0000
0000 -010
0000 0000
Q1 Q2 Q3 Q4
'0'