PIC16C773-I/SS Microchip Technology, PIC16C773-I/SS Datasheet - Page 37

IC MCU OTP 4KX14 A/D PWM 28SSOP

PIC16C773-I/SS

Manufacturer Part Number
PIC16C773-I/SS
Description
IC MCU OTP 4KX14 A/D PWM 28SSOP
Manufacturer
Microchip Technology
Series
PIC® 16Cr

Specifications of PIC16C773-I/SS

Program Memory Type
OTP
Program Memory Size
7KB (4K x 14)
Package / Case
28-SSOP
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 6x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC16C
Core
PIC
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
I2C/SPI/SSP/UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
22
Number Of Timers
3
Operating Supply Voltage
2.5 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
ICE2000, DM163022
Minimum Operating Temperature
- 40 C
On-chip Adc
6-ch x 12-bit
Controller Family/series
PIC16C
No. Of I/o's
22
Ram Memory Size
256Byte
Cpu Speed
20MHz
No. Of Timers
3
Embedded Interface Type
I2C, SPI, USART
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
309-1025 - ADAPTER 28-SSOP TO 28-DIP
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
3.6
The Parallel Slave Port is implemented on the
40/44-pin devices only.
PORTD operates as an 8-bit wide Parallel Slave Port,
or microprocessor port when control bit PSPMODE
(TRISE<4>) is set. In slave mode it is asynchronously
readable and writable by the external world through RD
control input pin RE0/RD and WR control input pin
RE1/WR.
It can directly interface to an 8-bit microprocessor data
bus. The external microprocessor can read or write the
PORTD latch as an 8-bit latch. Setting bit PSPMODE
enables port pin RE0/RD to be the RD input, RE1/WR
to be the WR input and RE2/CS to be the CS (chip
select) input. For this functionality, the corresponding
data direction bits of the TRISE register (TRISE<2:0>)
must be configured as inputs (set). The configuration
bits, PCFG3:PCFG0 (ADCON1<3:0>) must be config-
ured to make pins RE2:RE0 as digital I/O.
A write to the PSP occurs when both the CS and WR
lines are first detected low. A read from the PSP occurs
when both the CS and RD lines are first detected low.
FIGURE 3-14: PARALLEL SLAVE PORT WRITE WAVEFORMS
PORTD<7:0>
1999 Microchip Technology Inc.
PSPIF
Parallel Slave Port
OBF
CS
WR
RD
IBF
Q1
Q2
Q3
Advance Information
Q4
Q1
Q2
FIGURE 3-13: PORTD AND PORTE BLOCK
One bit of PORTD
Note: I/O pin has protection diodes to V
Data bus
Set interrupt flag
PSPIF (PIR1<7>)
Q3
WR
PORT
RD
PORT
Q4
Q
D
CK
DIAGRAM (PARALLEL SLAVE
PORT)
EN
Q1
EN
Q
D
PIC16C77X
Q2
Chip Select
Read
Write
Q3
DS30275A-page 37
TTL
DD
TTL
TTL
TTL
and V
Q4
SS
CS
WR
RD
RDx
pin
.

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