DSPIC30F2023-30I/PTD32 Microchip Technology, DSPIC30F2023-30I/PTD32 Datasheet - Page 3

• Manufacturer Part Number: DSPIC30F2023-30I/PTD32
• Description: IC DSPIC MCU/DSP 12K 44-TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F2023-30I/PTD32

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 12KB (4K x 24)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: Q4035438

37. PWM Module
38. PWM Module
39. Power Supply PWM: “On-the-fly” dead time
40. UART Module
41. UART Module
42. SPI Module
43. I
© 2008 Microchip Technology Inc.
The
temperatures below -20ºC.
In Push-Pull mode, with immediate updates
enabled, the PWM pins may become swapped.
adjustment
The dead time registers (DTRx/ALTDTRx) must be
modified only when the PWM is not running and
should not be modified “on-the-fly”.
The 16x baud clock signal on the BCLK pin is
present only when the module is transmitting.
When the UART is in 4x mode (BRGH = 1) and
using two Stop bits (STSEL = 1), it may sample the
first Stop bit instead of the second one.
The SPIxCON1 DISSCK bit does not influence
port functionality.
The BCL bit in I2CSTAT can be cleared only with
16-bit operation and can be corrupted with 1-bit or
8-bit operations on I2CSTAT.
2
C Module
PWM
module
may
not
operate
at
44. I
45. I
46. I
47. UART (FIFO Error)
48. PSV Operations
The following sections describe the errata and work
around to these errata, where they may apply.
dsPIC30F1010/202X
When the I
addressing using the same address bits (A10 and
A9) as other I
work as expected.
The 10-bit slave does not set the RBF flag or load
the I2CxRCV register on an address match if the
Least Significant bits of the address are the same
as the 7-bit reserved addresses.
If the I
with an address of 0x102, the I2CxRCV register
content for the lower address byte is 0x01 rather
than 0x02.
Under certain circumstances, the PERR and
FERR error bits may not be correct for all bytes in
the receive FIFO.
An address error trap occurs in certain addressing
modes when accessing the first four bytes of any
PSV page.
2
2
2
C Module: 10-bit addressing mode
C Module: 10-bit Addressing Mode
C Module: 10-bit Addressing Mode
2
C module is configured for a 10-bit slave
2
C module is configured for 10-bit
2
C device A10 and A9 bits may not
DS80290J-page 3