PIC18F2620-E/SO Microchip Technology, PIC18F2620-E/SO Datasheet - Page 144
![IC MCU FLASH 32KX16 28SOIC](/photos/6/59/65909/150-28-soic_sml.jpg)
PIC18F2620-E/SO
Manufacturer Part Number
PIC18F2620-E/SO
Description
IC MCU FLASH 32KX16 28SOIC
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F2221-ISO.pdf
(46 pages)
3.PIC18F2525-ISO.pdf
(412 pages)
4.PIC18F2525-ISO.pdf
(18 pages)
5.PIC18F2525-ISO.pdf
(18 pages)
6.PIC18F2525-ISO.pdf
(6 pages)
7.PIC18F2525-ISO.pdf
(6 pages)
8.PIC18LF4620-IP.pdf
(390 pages)
Specifications of PIC18F2620-E/SO
Program Memory Type
FLASH
Program Memory Size
64KB (32K x 16)
Package / Case
28-SOIC (7.5mm Width)
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
25
Eeprom Size
1K x 8
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3986 B
Interface Type
SPI, I2C, EUSART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
25
Number Of Timers
4
Operating Supply Voltage
4.2 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 10 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
I3DB18F4620 - BOARD DAUGHTER ICEPIC3
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
- PIC16F616T-ISL PDF datasheet
- PIC18F2221-ISO PDF datasheet #2
- PIC18F2525-ISO PDF datasheet #3
- PIC18F2525-ISO PDF datasheet #4
- PIC18F2525-ISO PDF datasheet #5
- PIC18F2525-ISO PDF datasheet #6
- PIC18F2525-ISO PDF datasheet #7
- PIC18LF4620-IP PDF datasheet #8
- Current page: 144 of 390
- Download datasheet (7Mb)
PIC18F2525/2620/4525/4620
15.3
In Compare mode, the 16-bit CCPRx register value is
constantly compared against either the TMR1 or TMR3
register pair value. When a match occurs, the CCPx pin
can be:
• driven high
• driven low
• toggled (high-to-low or low-to-high)
• remain unchanged (that is, reflects the state of the
The action on the pin is based on the value of the mode
select bits (CCPxM3:CCPxM0). At the same time, the
interrupt flag bit, CCPxIF, is set.
15.3.1
The user must configure the CCPx pin as an output by
clearing the appropriate TRIS bit.
FIGURE 15-2:
DS39626B-page 142
I/O latch)
Note:
Compare Mode
CCP PIN CONFIGURATION
Clearing the CCP2CON register will force
the RB3 or RC1 compare output latch
(depending on device configuration) to the
default low level. This is not the PORTB or
PORTC I/O data latch.
0
1
COMPARE MODE OPERATION BLOCK DIAGRAM
CCPR2H
CCPR1H
TMR1H
TMR3H
T3CCP1
Comparator
Comparator
CCPR1L
CCPR2L
TMR1L
TMR3L
Compare
Compare
Match
Match
0
1
Set CCP1IF
T3CCP2
Preliminary
Set CCP2IF
(Timer1/Timer3 Reset, A/D Trigger)
15.3.2
Timer1 and/or Timer3 must be running in Timer mode
or Synchronized Counter mode if the CCP module is
using the compare feature. In Asynchronous Counter
mode, the compare operation may not work.
15.3.3
When the Generate Software Interrupt mode is chosen
(CCPxM3:CCPxM0 = 1010), the corresponding CCPx
pin is not affected. Only a CCP interrupt is generated,
if enabled and the CCPxIE bit is set.
15.3.4
Both CCP modules are equipped with a Special Event
Trigger. This is an internal hardware signal generated
in Compare mode to trigger actions by other modules.
The Special Event Trigger is enabled by selecting
the
(CCPxM3:CCPxM0 = 1011).
For either CCP module, the Special Event Trigger resets
the timer register pair for whichever timer resource is
currently assigned as the module’s time base. This
allows the CCPRx registers to serve as a programmable
period register for either timer.
The Special Event Trigger for CCP2 can also start an
A/D conversion. In order to do this, the A/D converter
must already be enabled.
(Timer1/Timer3 Reset)
Special Event Trigger
Special Event Trigger
CCP1CON<3:0>
CCP2CON<3:0>
Compare
Output
Logic
Output
4
Logic
4
TIMER1/TIMER3 MODE SELECTION
SOFTWARE INTERRUPT MODE
SPECIAL EVENT TRIGGER
Special
S
R
S
R
Q
Q
2004 Microchip Technology Inc.
Output Enable
Output Enable
Event
TRIS
TRIS
Trigger
CCP1 pin
CCP2 pin
mode
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