ATMEGA645-16MU Atmel, ATMEGA645-16MU Datasheet - Page 95

• Manufacturer Part Number: ATMEGA645-16MU
• Description: IC AVR MCU FLASH 64K 64-QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA645-16MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATMEGA64x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: SPI, UART, USI
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Package: 64MLF EP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 16 MHz
• For Use With: ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.8
2570M–AVR–04/11
Timer/Counter Timing Diagrams
•
The Timer/Counter is a synchronous design and the timer clock (clk
clock enable signal in the following figures. The figures include information on when Interrupt
Flags are set.
shows the count sequence close to the MAX value in all modes other than phase correct PWM
mode.
Figure 14-8. Timer/Counter Timing Diagram, no Prescaling
Figure 14-9
Figure 14-9. Timer/Counter Timing Diagram, with Prescaler (f
Figure 14-10
Figure 14-10. Timer/Counter Timing Diagram, Setting of OCF0A, with Prescaler (f
The timer starts counting from a value higher than the one in OCR0A, and for that reason
misses the Compare Match and hence the OCn change that would have happened on the
way up.
TCNTn
TCNTn
TCNTn
(clk
(clk
(clk
OCRnx
OCFnx
TOVn
TOVn
clk
clk
clk
clk
clk
clk
I/O
I/O
I/O
I/O
I/O
I/O
Tn
Tn
Tn
/1)
/8)
/8)
shows the same timing data, but with the prescaler enabled.
shows the setting of OCF0A in all modes except CTC mode.
Figure 14-8
OCRnx - 1
MAX - 1
MAX - 1
contains timing data for basic Timer/Counter operation. The figure
OCRnx
MAX
MAX
ATmega325/3250/645/6450
OCRnx Value
OCRnx + 1
BOTTOM
BOTTOM
clk_I/O
/8)
T0
) is therefore shown as a
BOTTOM + 1
BOTTOM + 1
OCRnx + 2
clk_I/O
/8)
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