PIC24FJ64GB002-I/ML Microchip Technology, PIC24FJ64GB002-I/ML Datasheet - Page 286

• Manufacturer Part Number: PIC24FJ64GB002-I/ML
• Description: IC MCU 16BIT 64KB FLASH 28QFN
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 24Fr

Specifications of PIC24FJ64GB002-I/ML

• Program Memory Type: FLASH
• Program Memory Size: 64KB (22K x 24)
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 19
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC24FJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C/IrDA/SPI/UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 19
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DM240011
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 9-ch x 10-bit
• Controller Family/series: PIC24
• Ram Memory Size: 8KB
• Cpu Speed: 32MHz
• No. Of Timers: 5
• Embedded Interface Type: I2C, LIN, SPI, UART, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC24FJ64GB004 FAMILY
When waking up from Sleep with the regulator
disabled, T
To decrease the device wake-up time when operating
with the regulator disabled, the PMSLP bit can be set.
26.2.3
When
PIC24FJ64GB004 family devices also have a simple
brown-out capability. If the voltage supplied to the reg-
ulator is inadequate to maintain the tracking level, the
regulator Reset circuitry will generate a Brown-out
Reset. This event is captured by the BOR flag bit
(RCON<1>). The brown-out voltage specifications are
provided in Section 7. “Reset” (DS39712) in the
“PIC24F Family Reference Manual”.
26.2.4
The on-chip regulator is designed to meet the power-up
requirements for the device. If the application does not
use the regulator, then strict power-up conditions must
be adhered to. While powering up, V
never exceed V
26.2.5
When enabled, the on-chip regulator always consumes
a small incremental amount of current over I
including when the device is in Sleep mode, even
though the core digital logic does not require power. To
provide additional savings in applications where power
resources are critical, the regulator automatically
places itself into Standby mode whenever the device
goes into Sleep mode by removing power from the
Flash program memory. This feature is controlled by
the PMSLP bit (RCON<8>). By default, this bit is
cleared, which enables Standby mode.
For PIC24FJ64GB004 family devices, the time
required for regulator wake-up from Standby mode is
controlled by the WUTSEL<1:0> Configuration bits
(CW3<11:10>). The default wake-up time for all
devices is 190 μs, which is a Legacy mode provided to
match older PIC24F device wake-up times.
Implementing the WUTSEL Configuration bits provides
a fast wake-up option. When WUTSEL<1:0> = 01, the
regulator wake-up time is T
When the regulator’s Standby mode is turned off
(PMSLP = 1), Flash program memory stays powered in
Sleep mode. That enables device wake-up without
waiting for T
consumption,
approximately 40 μA higher than what it would be if the
regulator was allowed to enter Standby mode.
DS39940C-page 284
Note:
the
PM
ON-CHIP REGULATOR AND BOR
POWER-UP REQUIREMENTS
For more information, see Section 29.0
“Electrical Characteristics”.
VOLTAGE REGULATOR STANDBY
MODE
PM
is used to determine the wake-up time.
. With PMSLP set, however, the power
DD
while
on-chip
by 0.3 volts.
in
PM
regulator
Sleep
, 10 μs.
mode,
is
DDCORE
enabled,
will
DD
must
/I
Preliminary
PD
be
,
26.3
For PIC24FJ64GB004 family devices, the WDT is
driven by the LPRC Oscillator. When the WDT is
enabled, the clock source is also enabled.
The nominal WDT clock source from LPRC is 31 kHz.
This feeds a prescaler that can be configured for either
5-bit (divide-by-32) or 7-bit (divide-by-128) operation.
The prescaler is set by the FWPSA Configuration bit.
With a 31 kHz input, the prescaler yields a nominal
WDT time-out period (T
4 ms in 7-bit mode.
A variable postscaler divides down the WDT prescaler
output and allows for a wide range of time-out periods.
The postscaler is controlled by the WDTPS<3:0>
Configuration bits (CW1<3:0>), which allow the selec-
tion of a total of 16 settings, from 1:1 to 1:32,768. Using
the prescaler and postscaler time-out periods, ranging
from 1 ms to 131 seconds can be achieved.
The WDT, prescaler and postscaler are reset:
• On any device Reset
• On the completion of a clock switch, whether
• When a PWRSAV instruction is executed
• When the device exits Sleep or Idle mode to
• By a CLRWDT instruction during normal execution
If the WDT is enabled, it will continue to run during
Sleep or Idle modes. When the WDT time-out occurs,
the device will wake the device and code execution will
continue from where the PWRSAV instruction was
executed. The corresponding SLEEP or IDLE bits
(RCON<3:2>) will need to be cleared in software after
the device wakes up.
The WDT Flag bit, WDTO (RCON<4>), is not auto-
matically cleared following a WDT time-out. To detect
subsequent WDT events, the flag must be cleared in
software.
invoked by software (i.e., setting the OSWEN bit
after changing the NOSC bits) or by hardware
(i.e., Fail-Safe Clock Monitor)
(i.e., Sleep or Idle mode is entered)
resume normal operation
Note:
Watchdog Timer (WDT)
The CLRWDT and PWRSAV instructions
clear the prescaler and postscaler counts
when executed.
© 2009 Microchip Technology Inc.
WDT
) of 1 ms in 5-bit mode, or