DSPIC33FJ64GS608-E/PT Microchip Technology, DSPIC33FJ64GS608-E/PT Datasheet - Page 36

• Manufacturer Part Number: DSPIC33FJ64GS608-E/PT
• Description: MCU/DSP 16BIT 64KB FLASH 80TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ64GS608-E/PT

• Program Memory Type: FLASH
• Program Memory Size: 64KB (64K x 8)
• Package / Case: 80-TFQFP
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, QEI, POR, PWM, WDT
• Number Of I /o: 74
• Ram Size: 9K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 18x10b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC33F
• Core: dsPIC
• Numeric And Arithmetic Format: Fixed-Point or Floating-Point
• Instruction Set Architecture: Harvard
• Device Million Instructions Per Second: 40 MIPs
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 74
• Data Ram Size: 4 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
• Interface Type: I2C, SPI, UART
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 18 Channel
• On-chip Dac: 10 bit, 4 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
3.3
The
dsPIC33FJ64GS406/606/608/610 features a 17-bit by
17-bit single-cycle multiplier that is shared by both the
MCU ALU and DSP engine. The multiplier can perform
signed, unsigned and mixed sign multiplication. Using a
17-bit by 17-bit multiplier for 16-bit by 16-bit multiplication
not only allows you to perform mixed sign multiplication,
it also achieves accurate results for special operations,
such as (-1.0) x (-1.0).
FIGURE 3-1:
DS70591C-page 36
Control Block
PSV & Table
Data Access
Program Memory
Special MCU Features
Address Latch
dsPIC33FJ32GS406/606/608/610
Data Latch
23
23
Controller
Interrupt
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 CPU
CORE BLOCK DIAGRAM
23
to Various Blocks
Control Signals
Control
Stack
Logic
Instruction
Decode &
PCU
Program Counter
Control
24
8
PCH
Control
Logic
Loop
16
PCL
and
Preliminary
Divide Support
DSP Engine
16
Y Data Bus
X Data Bus
Instruction Reg
Data Latch
ROM Latch
Address Generator Units
Address
X RAM
Latch
The
dsPIC33FJ64GS406/606/608/610 supports 16/16 and
32/16 divide operations, both fractional and integer. All
divide instructions are iterative operations. They must be
executed within a REPEAT loop, resulting in a total
execution time of 19 instruction cycles. The divide
operation can be interrupted during any of those
19 cycles without loss of data.
A 40-bit barrel shifter is used to perform up to a 16-bit
left or right shift in a single cycle. The barrel shifter can
be used by both MCU and DSP instructions.
16
16
Data Latch
W Register Array
Address
Y RAM
Latch
dsPIC33FJ32GS406/606/608/610
EA MUX
16 x 16
16
16
16
16-Bit ALU
16
16
 2010 Microchip Technology Inc.
16
16
To Peripheral Modules
16
and