PIC18F6490-I/PT Microchip Technology, PIC18F6490-I/PT Datasheet - Page 232
PIC18F6490-I/PT
Manufacturer Part Number
PIC18F6490-I/PT
Description
IC PIC MCU FLASH 8KX16 64TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F6310-IPT.pdf
(28 pages)
3.PIC18F6390-IPT.pdf
(414 pages)
4.PIC18F6390-IPT.pdf
(16 pages)
5.PIC18F6390-IPT.pdf
(12 pages)
6.PIC18F6390-IPT.pdf
(6 pages)
7.PIC18F6390-IPT.pdf
(4 pages)
8.PIC18F8490-IPT.pdf
(412 pages)
Specifications of PIC18F6490-I/PT
Program Memory Type
FLASH
Program Memory Size
16KB (8K x 16)
Package / Case
64-TFQFP
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, LCD, POR, PWM, WDT
Number Of I /o
50
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
SPI/I2C/EUSART/AUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
50
Number Of Timers
4
Operating Supply Voltage
4.2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183028
Minimum Operating Temperature
- 25 C
On-chip Adc
12-ch x 10-bit
Package
64TQFP
Device Core
PIC
Family Name
PIC18
Maximum Speed
40 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT64PT5 - SOCKET TRAN ICE 64MQFP/TQFPDM163028 - BOARD DEMO PICDEM LCDAC164319 - MODULE SKT MPLAB PM3 64TQFPDV007003 - PROGRAMMER UNIVERSAL PROMATE II
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F6490-I/PT
Manufacturer:
RELPOL
Quantity:
12 000
Company:
Part Number:
PIC18F6490-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC18F6490-I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC16F616T-ISL PDF datasheet
- PIC18F6310-IPT PDF datasheet #2
- PIC18F6390-IPT PDF datasheet #3
- PIC18F6390-IPT PDF datasheet #4
- PIC18F6390-IPT PDF datasheet #5
- PIC18F6390-IPT PDF datasheet #6
- PIC18F6390-IPT PDF datasheet #7
- PIC18F8490-IPT PDF datasheet #8
- Current page: 232 of 414
- Download datasheet (7Mb)
PIC18F6390/6490/8390/8490
17.4.2
The operation of the Synchronous Master and Slave
modes is identical except in the case of Sleep, or any
Idle mode and bit SREN, which is a “don’t care” in
Slave mode.
If receive is enabled by setting the CREN bit prior to
entering Sleep, or any Idle mode, then a word may be
received while in this low-power mode. Once the word
is received, the RSR register will transfer the data to the
RCREG2 register; if the RC2IE enable bit is set, the
interrupt generated will wake the chip from low-power
mode. If the global interrupt is enabled, the program will
branch to the interrupt vector.
TABLE 17-9:
DS39629C-page 230
INTCON
PIR3
PIE3
IPR3
RCSTA2
RCREG2
TXSTA2
SPBRG2
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception.
Name
AUSART SYNCHRONOUS
SLAVE RECEPTION
AUSART2 Receive Register
AUSART2 Baud Rate Generator Register
GIE/GIEH PEIE/GIEL TMR0IE
CSRC
SPEN
Bit 7
REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
—
—
—
LCDIF
LCDIE
LCDIP
Bit 6
RX9
TX9
RC2IE
RC2IP
RC2IF
SREN
TXEN
Bit 5
INT0IE
CREN
TX2IF
TX2IE
TX2IP
SYNC
Bit 4
ADDEN
To set up a Synchronous Slave Reception:
1.
2.
3.
4.
5.
6.
7.
8.
9.
RBIE
Bit 3
—
—
—
—
Enable the synchronous master serial port by
setting bits, SYNC and SPEN, and clearing bit,
CSRC.
If interrupts are desired, set enable bit, RC2IE.
If 9-bit reception is desired, set bit, RX9.
To enable reception, set enable bit, CREN.
Flag bit, RC2IF, will be set when reception is
complete. An interrupt will be generated if
enable bit, RC2IE, was set.
Read the RCSTA2 register to get the 9th bit (if
enabled) and determine if any error occurred
during reception.
Read the 8-bit received data by reading the
RCREG2 register.
If any error occurred, clear the error by clearing
bit, CREN.
If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
TMR0IF
BRGH
FERR
Bit 2
—
—
—
INT0IF
OERR
TRMT
© 2007 Microchip Technology Inc.
Bit 1
—
—
—
RX9D
TX9D
RBIF
Bit 0
—
—
—
on Page
Values
Reset
59
61
61
61
63
63
63
63
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