DSPIC30F5015T-30I/PT Microchip Technology, DSPIC30F5015T-30I/PT Datasheet

IC DSPIC MCU/DSP 66K 64TQFP

DSPIC30F5015T-30I/PT

Manufacturer Part Number
DSPIC30F5015T-30I/PT
Description
IC DSPIC MCU/DSP 66K 64TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr

Specifications of DSPIC30F5015T-30I/PT

Core Processor
dsPIC
Core Size
16-Bit
Speed
30 MIPs
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
52
Program Memory Size
66KB (22K x 24)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TFQFP
For Use With
AC30F008 - MODULE SKT FOR DSPIC30F 64TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DSPIC30F5015T-30I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
DSPIC30F5015T-30I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
The dsPIC30F5015/5016 (Rev. A0) samples you have
received were found to conform to the specifications
and functionality described in the following documents:
• DS70157 – “dsPIC30F/33F Programmer’s
• DS70149 – “dsPIC30F5015/5016 Data Sheet”
• DS70046 – “dsPIC30F Family Reference Manual”
The exceptions to the specifications in the documents
listed above are described in this section. These
exceptions are described for the specific devices listed
below:
• dsPIC30F5015
• dsPIC30F5016
These devices may be identified by the following
message that appears in the MPLAB
Window under MPLAB IDE, when a “Reset and
Connect” operation is performed within MPLAB IDE:
Setting Vdd source to target
Target Device dsPIC30F5016 found,
revision = Rev A0
...Reading ICD Product ID
Running ICD Self Test
...Passed
MPLAB ICD 2 Ready
The errata described in this section will be addressed
in
dsPIC30F5016 devices.
© 2008 Microchip Technology Inc.
Reference Manual”
future
revisions
dsPIC30F5015/5016 Rev. A0 Silicon Errata
of
dsPIC30F5015
®
ICD 2 Output
dsPIC30F5015/5016
and
Silicon Errata Summary
The following list summarizes the errata described in
this document:
1.
2.
3.
4.
5.
6.
7.
8.
9.
DISI Instruction
The DISI instruction will not disable interrupts if a
DISI instruction is executed in the same
instruction
decrements to zero.
Output Compare Module
The output compare module will produce a glitch
on the output when an I/O pin is initially set high
and the module is configured to drive the pin low at
a specified time.
Output Compare Module in PWM Mode
Output compare will produce a glitch when
loading 0% duty cycle in PWM mode. It will also
miss the next compare after the glitch.
Quadrature Encoder Interface Module
The Index Pulse Reset mode of the QEI does not
work properly when used along with count error
detection. When counting upwards, the POSCNT
register will increment one extra count after the
index pulse is received. The extra count will
generate a false count error interrupt.
INT0, ADC and Sleep Mode
ADC event triggers from the INT0 pin will not
wake-up the device from Sleep mode if the SMPI
bits are non-zero.
10-bit ADC: Sampling Rate
The 10-bit Analog-to-Digital Converter (ADC) has
a maximum sampling rate of 750 ksps.
Quadrature Encoder Interface (QEI) Module
The QEI module does not generate an interrupt in
a particular overflow condition.
Sleep Mode
Execution of the Sleep instruction (PWRSAV #0)
may cause incorrect program operation after the
device wakes up from Sleep. The current
consumption during Sleep may also increase
beyond the specifications listed in the device data
sheet.
I
The I
operating as an I
2
C Module
2
C module loses incoming data bytes when
cycle
2
C slave.
that
the
DS80247H-page 1
DISI
counter

Related parts for DSPIC30F5015T-30I/PT

DSPIC30F5015T-30I/PT Summary of contents

Page 1

... MPLAB ICD 2 Ready The errata described in this section will be addressed in future revisions of dsPIC30F5015 dsPIC30F5016 devices. © 2008 Microchip Technology Inc. dsPIC30F5015/5016 Silicon Errata Summary The following list summarizes the errata described in this document: 1. DISI Instruction The DISI instruction will not disable interrupts if a ...

Page 2

... When these events occur, the output compare module will drive the pin low for one instruction cycle (T ) after the module is enabled. CY Work around None. However, the user may use a Timer interrupt and write to the associated PORT register to control the pin manually. © 2008 Microchip Technology Inc. ...

Page 3

... QEI interrupt handler and used as an offset value to calculate the absolute position of the encoder disc with respect to the index pulse. © 2008 Microchip Technology Inc. dsPIC30F5015/5016 5. Module: INT0, ADC and Sleep Mode ADC event triggers from the INT0 pin will not ...

Page 4

... A/D Channels Configuration REF REF CH X ANx S/H ADC REF REF ANx S/H ADC ANx REF REF REF ANx S/H ADC ANx REF © 2008 Microchip Technology Inc. ...

Page 5

... User's code } void __attribute__((__interrupt__)) _QEIInterrupt(void) { IFSxbits.QEIIF = 0; POSCNT_b15 ^= 0x8000; // Overflow or Underflow } © 2008 Microchip Technology Inc. dsPIC30F5015/5016 Work around To prevent this condition from occurring, set MAXCNT to 0x7FFF, which will cause an interrupt to be generated by the QEI module. In addition, a global variable could be used to keep ...

Page 6

... Sleep mode. Example 2 described above would apply to a dsPIC30F5015 device. ; Ensure flag is reset ; Return from Interrupt Service Routine the function call would be following the or _GotoSleep demonstrates the work around © 2008 Microchip Technology Inc. ...

Page 7

... Note: The above work around is recommended for users for whom application hardware changes are not possible. © 2008 Microchip Technology Inc. dsPIC30F5015/5016 Work around 3: Instead of executing a PWRSAV #0 instruction to put the device into Sleep mode, perform a clock switch to the 32 kHz Low-Power (LP) Oscillator with a 64:1 postscaler mode ...

Page 8

... Module: Motor Control PWM – PWM Counter Register If the PTDIR bit is set (when PTMR is counting down), and the CPU execution is halted (after a breakpoint is reached), PTMR will start counting PTDIR was zero. Work around None. © 2008 Microchip Technology Inc slave interrupt 2 C nodes receive 2 ...

Page 9

... Clock Failure Status bit (OSCCON<3>). If this bit is clear, return from the trap service routine immediately and continue program execution. © 2008 Microchip Technology Inc. dsPIC30F5015/5016 15. Module: PSV Operations An address error trap occurs in certain addressing modes when accessing the first four bytes of an PSV page ...

Page 10

... For example, if the SDA and SCL pins are shared with the UART and SPI pins, and the UART has higher precedence on the port latch pin. DS80247H-page module is that have 2 C © 2008 Microchip Technology Inc. ...

Page 11

... Added silicon issues 13 and 14 (I C), and 15 (Timer). Removed silicon issue 3 (Using OSC2/RC15 pin for Digital I/O). Revision H (9/2008) 2 Replaced issues 9 and with issue 18 (I Added silicon issues 14 (PLL Lock Status Bit), 15 (PSV 2 Operations) and 16-18 (I C). © 2008 Microchip Technology Inc. dsPIC30F5015/5016 2 C). DS80247H-page 11 ...

Page 12

... NOTES: DS80247H-page 12 © 2008 Microchip Technology Inc. ...

Page 13

... PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...

Page 14

... Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-572-9526 Fax: 886-3-572-6459 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 © 2008 Microchip Technology Inc. 01/02/08 ...

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