PIC18F2431-I/SO Microchip Technology, PIC18F2431-I/SO Datasheet - Page 42
PIC18F2431-I/SO
Manufacturer Part Number
PIC18F2431-I/SO
Description
IC PIC MCU FLASH 8KX16 28SOIC
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F818-ISO.pdf
(6 pages)
3.PIC18F2331-ISO.pdf
(392 pages)
4.PIC18F2331-ISO.pdf
(8 pages)
5.PIC18F2331-ISO.pdf
(6 pages)
6.PIC18F2331-ISO.pdf
(16 pages)
7.PIC18LF2331-ISO.pdf
(40 pages)
8.PIC18F2431-ISP.pdf
(396 pages)
Specifications of PIC18F2431-I/SO
Program Memory Type
FLASH
Program Memory Size
16KB (8K x 16)
Package / Case
28-SOIC (7.5mm Width)
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, Power Control PWM, QEI, POR, PWM, WDT
Number Of I /o
24
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
EUSART/I2C/SPI/SSP
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
24
Number Of Timers
4
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM183021, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
5-ch x 10-bit
Package
28SOIC W
Device Core
PIC
Family Name
PIC18
Maximum Speed
40 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT28SO-1 - SOCKET TRANSITION 28SOIC 300MILI3-DB18F4431 - BOARD DAUGHTER ICEPIC3
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F2431-I/SO
Manufacturer:
MICROCHIP
Quantity:
2 000
Part Number:
PIC18F2431-I/SO
Manufacturer:
NXP/恩智浦
Quantity:
20 000
- PIC16F616T-ISL PDF datasheet
- PIC16F818-ISO PDF datasheet #2
- PIC18F2331-ISO PDF datasheet #3
- PIC18F2331-ISO PDF datasheet #4
- PIC18F2331-ISO PDF datasheet #5
- PIC18F2331-ISO PDF datasheet #6
- PIC18LF2331-ISO PDF datasheet #7
- PIC18F2431-ISP PDF datasheet #8
- Current page: 42 of 392
- Download datasheet (4Mb)
PIC18F2331/2431/4331/4431
If the IRCF bits and the INTSRC bit are all clear, the
INTOSC output is not enabled and the IOFS bit will
remain clear; there will be no indication of the current
clock source. The INTRC source is providing the
device clocks.
If the IRCF bits are changed from all clear (thus,
enabling the INTOSC output), or if INTSRC is set, the
IOFS bit becomes set after the INTOSC output
becomes stable. Clocks to the device continue while
the INTOSC source stabilizes, after an interval of
T
If the IRCF bits were previously at a non-zero value, or
if INTSRC was set before setting SCS1 and the
INTOSC source was already stable, the IOFS bit will
remain set.
FIGURE 4-3:
FIGURE 4-4:
DS39616D-page 42
IOBST
.
Note 1: Clock transition typically occurs within 2-4 T
Peripheral
Program
Counter
INTRC
OSC1
Clock
Clock
CPU
Note 1: T
Multiplexer
CPU Clock
Peripheral
PLL Clock
Program
INTOSC
Counter
Output
OSC1
Clock
2: Clock transition typically occurs within 2-4 T
Q1
SCS<1:0> bits Changed
Q2
TRANSITION TIMING TO RC_RUN MODE
PC
TRANSITION TIMING FROM RC_RUN MODE TO PRI_RUN MODE
OST
Q3
= 1024 T
Q4
Q1
OSC
Q1
1
; T
T
OST
PLL
(1)
PC
2
= 2 ms (approx). These intervals are not shown to scale.
Q2
Clock Transition
3
T
PLL (1)
OSTS bit Set
Q3
OSC
PC + 2
(1)
n-1
Q4
.
OSC
On transitions from RC_RUN mode to PRI_RUN mode,
the device continues to be clocked from the INTOSC
multiplexer while the primary clock is started. When the
primary clock becomes ready, a clock switch to the
primary clock occurs (see
switch is complete, the IOFS bit is cleared, the OSTS
bit is set and the primary clock is providing the device
clock. The IDLEN and SCS bits are not affected by the
switch. The INTRC source will continue to run if either
the WDT or the Fail-Safe Clock Monitor is enabled.
n
.
Q1
1
Transition
2
Clock
n-1 n
(2)
Q2
PC + 2
Q3
Q2
Q4
2010 Microchip Technology Inc.
Q3 Q4
Figure
Q1
Q1
PC + 4
4-4). When the clock
Q2
PC + 4
Q2
Q3
Q3
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