ATXMEGA32A4-MH Atmel, ATXMEGA32A4-MH Datasheet - Page 14

• Manufacturer Part Number: ATXMEGA32A4-MH
• Description: MCU AVR 32K FLASH 1.6V 44-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA32A4-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-VQFN Exposed Pad
• Processor Series: ATXMEGA32x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 4 KB
• Interface Type: I2C/SPI/USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 34
• Number Of Timers: 5
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12-ch x 12-bit
• On-chip Dac: 2-ch x 12-bit
• Package: 44VQFN EP
• Device Core: AVR
• Family Name: XMEGA
• Maximum Speed: 32 MHz
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA32A4-MU; ATXMEGA32A4-MU

7.7
8069Q–AVR–12/10
ATxmega16A4
ATxmega32A4
ATxmega64A4
ATxmega128A4
ATxmega16A4
ATxmega32A4
ATxmega64A4
ATxmega128A4
Devices
Devices
Flash and EEPROM Page Size
128 KB + 8 KB
16 KB + 4 KB
32 KB + 4 KB
64 KB + 4 KB
Flash
Size
EEPROM
The Flash Program Memory and EEPROM data memory are organized in pages. The pages are
word accessible for the Flash and byte accessible for the EEPROM.
Table 7-2 on page 14
operations are performed on one page at a time, while reading the Flash is done one byte at a
time. For Flash access the Z-pointer (Z[m:n]) is used for addressing. The most significant bits in
the address (FPAGE) give the page number and the least significant address bits (FWORD)
give the word in the page.
Table 7-2.
Table 7-3 on page 14
EEPROM write and erase operations can be performed one page or one byte at a time, while
reading the EEPROM is done one byte at a time. For EEPROM access the NVM Address Regis-
ter (ADDR[m:n]) is used for addressing. The most significant bits in the address (E2PAGE) give
the page number and the least significant address bits (E2BYTE) give the byte in the page.
Table 7-3.
Size
1 KB
1 KB
2 KB
2 KB
Page Size
(words)
128
128
128
256
Number of words and Pages in the Flash.
Number of Bytes and Pages in the EEPROM.
Page Size
FWORD
(Bytes)
Z[6:0]
Z[6:0]
Z[6:0]
Z[7:0]
shows the Flash Program Memory organization. Flash write and erase
32
32
32
32
shows EEPROM memory organization for the XMEGA A4 devices.
FPAGE
Z[13:7]
Z[14:7]
Z[15:7]
Z[16:8]
ADDR[4:0]
ADDR[4:0]
ADDR[4:0]
ADDR[4:0]
E2BYTE
128 KB
16 KB
32 KB
64 KB
Size
Application
No of Pages
ADDR[10:5]
ADDR[10:5]
ADDR[10:5]
ADDR[10:5]
E2PAGE
128
128
256
64
4 KB
8 KB
Size
4 KB
4 KB
XMEGA A4
No of Pages
Boot
No of Pages
32
32
64
64
16
16
16
16
14