PIC18F2520-I/ML Microchip Technology, PIC18F2520-I/ML Datasheet - Page 200
PIC18F2520-I/ML
Manufacturer Part Number
PIC18F2520-I/ML
Description
IC PIC MCU FLASH 16KX16 28QFN
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F2221-ISO.pdf
(46 pages)
3.PIC18F2420-IML.pdf
(412 pages)
4.PIC18F2420-IML.pdf
(16 pages)
5.PIC18F2420-IML.pdf
(8 pages)
6.PIC18F2420-IML.pdf
(6 pages)
7.PIC18F2420-IML.pdf
(8 pages)
8.PIC18F2420-IML.pdf
(4 pages)
9.PIC18F4420-IP.pdf
(390 pages)
Specifications of PIC18F2520-I/ML
Program Memory Type
FLASH
Program Memory Size
32KB (16K x 16)
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
25
Eeprom Size
256 x 8
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1.5 KB
Interface Type
EUSART/I2C/MSSP/SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
25
Number Of Timers
4
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM163022, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10-ch x 10-bit
Package
28QFN EP
Device Core
PIC
Family Name
PIC18
Maximum Speed
40 MHz
Data Rom Size
256 KB
Height
0.88 mm
Length
6 mm
Supply Voltage (max)
5.5 V
Supply Voltage (min)
4.2 V
Width
6 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
MCP3909RD-3PH1 - REF DESIGN MCP3909 3PH ENGY MTRXLT28QFN4 - SOCKET TRANS ICE 28QFN W/CABLEAC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F2520-I/ML
Manufacturer:
MICROCHI
Quantity:
20 000
- PIC16F616T-ISL PDF datasheet
- PIC18F2221-ISO PDF datasheet #2
- PIC18F2420-IML PDF datasheet #3
- PIC18F2420-IML PDF datasheet #4
- PIC18F2420-IML PDF datasheet #5
- PIC18F2420-IML PDF datasheet #6
- PIC18F2420-IML PDF datasheet #7
- PIC18F2420-IML PDF datasheet #8
- PIC18F4420-IP PDF datasheet #9
- Current page: 200 of 412
- Download datasheet (7Mb)
PIC18F2420/2520/4420/4520
17.4.17.2
During a Repeated Start condition, a bus collision
occurs if:
a)
b)
When the user deasserts SDA and the pin is allowed to
float high, the BRG is loaded with SSPADD<6:0> and
counts down to 0. The SCL pin is then deasserted and
when sampled high, the SDA pin is sampled.
FIGURE 17-29:
FIGURE 17-30:
DS39631E-page 198
A low level is sampled on SDA when SCL goes
from low level to high level.
SCL goes low before SDA is asserted low,
indicating that another master is attempting to
transmit a data ‘1’.
SDA
SCL
BCLIF
RSEN
S
SSPIF
SDA
SCL
RSEN
BCLIF
S
SSPIF
Bus Collision During a Repeated
Start Condition
BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)
BUS COLLISION DURING REPEATED START CONDITION (CASE 2)
SCL goes low before SDA,
set BCLIF. Release SDA and SCL.
T
BRG
Sample SDA when SCL goes high.
If SDA = 0, set BCLIF and release SDA and SCL.
masters can assert SDA at exactly the same time.
If SDA is low, a bus collision has occurred (i.e., another
master is attempting to transmit a data ‘0’, Figure 17-29).
If SDA is sampled high, the BRG is reloaded and begins
counting. If SDA goes from high-to-low before the BRG
times out, no bus collision occurs because no two
If SCL goes from high-to-low before the BRG times out
and SDA has not already been asserted, a bus collision
occurs. In this case, another master is attempting to
transmit a data ‘1’ during the Repeated Start condition,
see Figure 17-30.
If, at the end of the BRG time-out, both SCL and SDA
are still high, the SDA pin is driven low and the BRG is
reloaded and begins counting. At the end of the count,
regardless of the status of the SCL pin, the SCL pin is
driven low and the Repeated Start condition is
complete.
T
Cleared in software
© 2008 Microchip Technology Inc.
BRG
Interrupt cleared
in software
‘0’
‘0’
‘0’
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