DSPIC33FJ64GS610-E/PT Microchip Technology, DSPIC33FJ64GS610-E/PT Datasheet - Page 3

• Manufacturer Part Number: DSPIC33FJ64GS610-E/PT
• Description: MCU/DSP 16BIT 64KB FLASH 100TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ64GS610-E/PT

• Program Memory Type: FLASH
• Program Memory Size: 64KB (64K x 8)
• Package / Case: 100-TFQFP
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, QEI, POR, PWM, WDT
• Number Of I /o: 85
• Ram Size: 9K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 24x10b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC33F
• Core: dsPIC
• Numeric And Arithmetic Format: Fixed-Point or Floating-Point
• Instruction Set Architecture: Harvard
• Device Million Instructions Per Second: 40 MIPs
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 85
• Data Ram Size: 4 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
• Interface Type: I2C, SPI, UART
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 24 Channel
• On-chip Dac: 10 bit, 4 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Silicon Errata Issues
1. Module: ECAN
2. Module: Reserved
The issue in the previous version of the document has
been removed.
3. Module: SPI
© 2010 Microchip Technology Inc.
Note:
The WAKIF bit in the CxINTF register cannot be
cleared by software instruction after the device is
interrupted from Sleep due to activity on the CAN
bus.
When the device wakes up from Sleep due to CAN
bus activity, the ECAN module is placed in
operational mode. The ECAN event interrupt
occurs due to the WAKIF flag. Trying to clear the
flag in the Interrupt Service Routine (ISR) may not
clear the flag. The WAKIF bit being set will not
cause
execution.
Work around
Although the WAKIF bit does not clear, the device
Sleep and ECAN Wake function continue to work
as expected. If the ECAN event is enabled, the
CPU will enter the Interrupt Service Routine due to
the WAKIF flag getting set. The application can
maintain a secondary flag, which tracks the device
Sleep and Wake events.
Affected Silicon Revisions
The ASS1 pin is provided as an alternative pin for
the slave select function of the SPI1 module.
However, the alternate slave select function
(ASS1) on this pin does not work. All other
functions multiplexed on the same pin work as
expected.
Work around
Use the SS1 pin for the slave select function.
Affected Silicon Revisions
A0
A0
X
X
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. The shaded
column in the “Affected Silicon Revisions”
table included in each issue indicates that
the issue applies to the most current
revision of silicon (A0).
repetitive
Interrupt
Service
Routine
4. Module: JTAG
5. Module: PWM
The boundary scan cells for the RD3 and RD13
pins are swapped. When running the boundary
scan test, an input to the RD3 pin excites the RD13
pin, and vice versa.
This erratum does not affect any other functionality
on the RD3 and RD13 pins.
Work around
None.
Affected Silicon Revisions
The SYNCO2 pin can be used to transmit
synchronization pulses to generate an identical
PWM time base on another device. However, the
SYNCO2 function does not work as expected. As
a result of this erratum, the secondary master time
base cannot be used for synchronizing a slave
device.
All other functions multiplexed on the same pin
work as expected.
Work around
A spare PWMxL/PWMxH pin can be used as the
synchronization source output instead of the
SYNCO2 pin using the following procedure:
1.
2.
3.
Affected Silicon Revisions
A0
A0
X
X
Configure the spare PWMxL/PWMxH pin to
Set up the duty cycle for the spare PWMxL/
PWMxH pin to the desired pulse width for
the synchronization signal (typically 100 ns
at the highest PWM resolution).
Connect the spare PWMxL/PWMxH pin to
the synchronization input of the slave PWM
generator.
operate on the same time base, period, and
phase as the synchronizing (or reference)
PWM channel.
DS80489C-page 3