PIC24HJ64GP504-I/PT Microchip Technology, PIC24HJ64GP504-I/PT Datasheet - Page 261

IC PIC MCU FLASH 64K 44TQFP

PIC24HJ64GP504-I/PT

Manufacturer Part Number
PIC24HJ64GP504-I/PT
Description
IC PIC MCU FLASH 64K 44TQFP
Manufacturer
Microchip Technology
Series
PIC® 24Hr

Specifications of PIC24HJ64GP504-I/PT

Core Size
16-Bit
Program Memory Size
64KB (22K x 24)
Core Processor
PIC
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, PMP, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
35
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 13x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Controller Family/series
PIC24
No. Of I/o's
35
Ram Memory Size
4KB
Cpu Speed
40MIPS
No. Of Timers
7
No. Of Pwm Channels
4
Embedded Interface Type
CAN, I2C, SPI, UART
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
876-1004 - PIC24 BREAKOUT BOARDDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC24HJ64GP504-I/PT
Manufacturer:
MICROCHIP
Quantity:
1 001
Part Number:
PIC24HJ64GP504-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
25.0
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and
PIC24HJ128GPX02/X04 devices include the following
features intended to maximize application flexibility and
reliability, and minimize cost through elimination of
external components:
• Flexible configuration
• Watchdog Timer (WDT)
• Code Protection and CodeGuard™ Security
• JTAG Boundary Scan Interface
• In-Circuit Serial Programming™ (ICSP™)
• In-Circuit emulation
TABLE 25-1:
© 2009 Microchip Technology Inc.
0xF80000 FBS
0xF80002 FSS
0xF80004 FGS
0xF80006 FOSCSEL
0xF80008 FOSC
0xF8000A FWDT
0xF8000C FPOR
0xF8000E FICD
0xF80010 FUID0
0xF80012 FUID1
0xF80014 FUID2
0xF80016 FUID3
Legend: — = unimplemented bit, read as ‘0’.
Note 1:
Address
Note 1: This data sheet summarizes the features
2:
3:
2: Some registers and associated bits
SPECIAL FEATURES
This Configuration register is not available and reads as 0xFF on PIC24HJ32GP302/304 devices.
These bits are reserved and always read as ‘1’.
These bits are reserved for use by development tools and must be programmed as ‘1’.
of
PIC24HJ64GPX02/X04
PIC24HJ128GPX02/X04
devices. It is not intended to be a compre-
hensive reference source. To comple-
ment the information in this data sheet,
refer to the “dsPIC33F/PIC24H Family
Reference Manual”. Please see the
Microchip web site (www.microchip.com)
for the latest dsPIC33F/PIC24H Family
Reference Manual sections.
described in this section may not be avail-
able on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
Name
(1)
DEVICE CONFIGURATION REGISTER MAP
the
FWDTEN WINDIS
IESO
Bit 7
PIC24HJ32GP302/304,
FCKSM<1:0>
Reserved
RBS<1:0>
RSS<1:0>
Reserved
Bit 6
families
(3)
(2)
IOL1WAY
and
JTAGEN
Preliminary
of
Bit 5
User Unit ID Byte 0
User Unit ID Byte 1
User Unit ID Byte 2
User Unit ID Byte 3
WDTPRE
25.1
The Configuration bits can be programmed (read as
‘0’), or left unprogrammed (read as ‘1’), to select
various device configurations. These bits are mapped
starting at program memory location 0xF80000.
The individual Configuration bit descriptions for the
Configuration registers are shown in Table 25-1.
Note that address 0xF80000 is beyond the user program
memory space. It belongs to the configuration memory
space (0x800000-0xFFFFFF), which can only be
accessed using table reads and table writes.
To prevent inadvertent configuration changes during
code execution, all programmable Configuration bits
are write-once. After a bit is initially programmed during
a power cycle, it cannot be written to again. Changing
a device configuration requires that power to the device
be cycled.
The Device Configuration register map is shown in
Table 25-1.
ALTI2C
Bit 4
Configuration Bits
Bit 3
BSS<2:0>
SSS<2:0>
OSCIOFNC POSCMD<1:0>
WDTPOST<3:0>
Bit 2
GSS<1:0>
FNOSC<2:0>
FPWRT<2:0>
DS70293D-page 261
Bit 1
ICS<1:0>
GWRP
BWRP
SWRP
Bit 0

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